Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: CDC I, Location: Bangalore, Karnataka

Page: 7

RTL Design - Peripheral(Sr Staff)

is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding...

Company: Qualcomm
Posted Date: 28 Sep 2025

Staff Digital Design Engineer

(plus) Expertise in Linting, CDC, and RDC verification Constraint development using SDC and timing closure techniques Low-power...

Company: onsemi
Posted Date: 27 Sep 2025

AMS Verification engineer

. Familiarity with formal verification, linting, or CDC (Clock Domain Crossing) tools. Experience in a specific domain...

Company: Quest Global
Posted Date: 27 Sep 2025

Soc DFT Design Engineer

, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good...

Posted Date: 23 Sep 2025

Digital Design Lead

review, CDC, LINT, LEC, CLP, Synthesis etc. Customer Support & Governance Analyze and Recommend improvements... experience Familiar with design process – RTL coding, LINT, CDC, RDC, Synthesis, etc. Exceptional interpersonal...

Posted Date: 20 Sep 2025

SoC DV CPU

with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Exposure to CDC DV, Post...

Company: Quest Global
Posted Date: 17 Sep 2025

Technical Lead II - VLSI ML

Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...

Company: UST
Posted Date: 13 Sep 2025

Technical Lead II - VLSI MD

Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...

Company: UST
Posted Date: 13 Sep 2025

Technical Lead I - VLSI PD CAD

: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus...

Company: UST
Posted Date: 13 Sep 2025

Associate III - VLSI IO Design

Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...

Company: UST
Posted Date: 13 Sep 2025

Technical Lead II - VLSI m-CD

Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...

Company: UST
Posted Date: 12 Sep 2025

RTL Design(DSP)-Sr Lead

. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF...

Company: Qualcomm
Posted Date: 12 Sep 2025

RTL Design(DSP) - Sr Staff

), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage...

Company: Qualcomm
Posted Date: 12 Sep 2025

RTL Design(DSP)-Sr Lead

. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF...

Company: Qualcomm
Posted Date: 12 Sep 2025