Senior UVM Digital Verification Engineer Location: Cambridge, MA Security Clearance: SECRET Our Digital Design Team... is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs...
Senior Principal UVM Digital Verification Engineer - FPGA/ASIC Security Systems Join our elite Digital Design Team... as a Senior Principal UVM Digital Verification Engineer, where you'll lead groundbreaking verification initiatives for advanced...
Senior Design Verification Engineer Remote / work from any US location US Citizen or US Permanent Resident Full-time.../employee + Bonus, Benefits, 401k, Stock Options Responsibilities: Develop and execute verification plans for digital...
. Distributed power architectures. Schematic capture. PCB layout. Spice. MATLAB. Simulink. UVM Digital Verification (Senior... Digital Systems Design (Senior – Principal): Fluent in SystemVerilog, Verilog or VHDL and familiar with LINT. Architectures...