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Keywords: SoC RTL Design Engineer, Location: Bangalore, Karnataka

Page: 3

Sr. Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting...: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly...

Posted Date: 02 Jul 2025

Sr. Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting...: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly...

Posted Date: 02 Jul 2025

Physical Design EMIR Engineer

_ SILICON DESIGN ENGINEER 2 THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge... will work on block level SoC electrical signoff convergence with physical design engineers. The candidate will be highly...

Posted Date: 02 Jul 2025

Sr Lead High-Speed Interface PHY IP Digital Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... experience of 4 to 7 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power...

Company: Qualcomm
Posted Date: 29 Jun 2025

PMTS Silicon Design Engineer

_ PMTS SILICON DESIGN ENGINEER We are currently seeking a highly skilled 15+ years Performance Verification engineers... with Arch, design, SOC, Post Silicon, Workload , Driver teams Requirements: BS +12 years or MS +10 years work experience...

Posted Date: 26 Jun 2025

DFT PMTS Silicon Design Engineer

_ AECG ASIC DFx - PMTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD... and extensive experience in DFT methodologies, particularly in the context of SoC design and development. THE PERSON...

Posted Date: 26 Jun 2025

ASIC Engineer, Design

, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams... to deliver comprehensive solutions for various technical domains. ASIC Engineer, Design Responsibilities Architecture...

Company: Meta
Posted Date: 26 Jun 2025

Design Verification Engineer

verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively... with other teams to deliver comprehensive solutions for various technical domains. Design Verification Engineer Responsibilities...

Company: Meta
Posted Date: 25 Jun 2025

MTS Silicon Design Engineer

, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT..._ Front-End Silicon Design & Integration (FEINT) Engineer The role: A Front-End Silicon Design and Integration (FEINT...

Posted Date: 19 Jun 2025

SERDES PHY Analog Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY...

Company: Qualcomm
Posted Date: 19 Jun 2025

Serdes PHY Analog Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY...

Company: Qualcomm
Posted Date: 19 Jun 2025

ASIC Design Engineer

of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers... Architecture and Design of custom IPs for integration into SOC's. Design & Develop RTL for Interfaces, Power Management, Clocking...

Company: Amazon
Posted Date: 19 Jun 2025

ASIC DFx - MTS Silicon Design Engineer

_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD...) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer...

Posted Date: 15 Jun 2025

Staff Digital Design Engineer

by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding..., ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . Position: Staff Engineer...

Posted Date: 13 Jun 2025

SMTS Silicon Design Engineer

_ SMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team... of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals...

Posted Date: 11 Jun 2025

SMTS Silicon Design Engineer

_ SMTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer... RTL to GDS implementation of complex IPs and supporting the SOC customers Working with RTL team to resolve timing...

Posted Date: 10 Jun 2025

SMTS Silicon Design Engineer

_ SMTS SILICON DESIGN ENGINEER As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design... and implementation of advanced semiconductor chips. Working closely with RTL designers, physical design teams, and other cross-functional...

Posted Date: 03 Jun 2025

Senior Staff Physical Design Engineer

. What You Can Expect As a Senior Staff Physical Design Engineer (PnR), you will be part of our Implementation team and responsible... such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the...

Company: Marvell
Posted Date: 31 May 2025

Physical design engineer

: As a Physical Design Engineer at Intverse, you will be responsible for the implementation of intricate designs from RTL (Register...Position: Physical Design Engineer Company: Intverse Location: Bangalore, Chennai, Pune, Noida Overview...

Company: Tek Spikes
Posted Date: 27 May 2025

Principal Physical Design Engineer

checks Low Power design & Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture... and Security, in the technology nodes across 3nm/5nm/7nm and more. What You Can Expect As a Principal Physical Design Engineer...

Company: Marvell
Posted Date: 24 May 2025