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Keywords: ASIC RTL / Soc Design Lead, Location: Bangalore, Karnataka

Page: 3

STA / Synthesis Engineer

_ SMTS SILICON DESIGN ENGINEER(Timing Constraints/STA Signoff Technical Lead) THE ROLE: As a member of the AECG ASIC...) and closure for 2–3 SoC projects from RTL to tape-out. Proficient in analyzing SoC architecture to derive appropriate timing...

Posted Date: 21 Jun 2025

Staff GPU Verification Engineer

methodology Have the opportunity to lead, coach and mentor other members of the team Participate in design and verification... of ASIC design methodologies, flows and tools Be able to plan, estimate and track your own work Experience working...

Posted Date: 08 Jun 2025

Principal GPU Verification Engineer

verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification... flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking...

Posted Date: 03 Jun 2025