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Keywords: ASIC Timing Engineer, Location: Santa Clara, CA

Page: 2

Senior Post Silicon Feature Development Engineer

Hardware Engineer to join our Silicon Solutions Group. In this role, you will lead system-design efforts to improve... bring-up plans. Lead system design partnering with architecture, software, chip/board designers, ASIC, and operations team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Jan 2026

Silicon Design Engineer

your career. Job Role and Responsibility: AMD, Inc., is hiring Silicon Design Engineer to Research, design, develop, and/or test.... Perform definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic...

Posted Date: 25 Jan 2026

MTS Silicon Design Engineer

your career. Job Role and Responsibility: AMD, Inc. is hiring MTS Silicon Design Engineer to Oversee definition, design..., verification, and/or documentation for ASIC development of Alert behavior for memory controller for DDR5. Determine architecture...

Posted Date: 25 Jan 2026

Product Development Engineer

your career. Job Role and Responsibility: AMD, Inc., is hiring Product Development Engineer to Drive complex data-based debug... for collecting and processing log events from semiconductor design tools (e.g., simulation outputs, synthesis logs, timing reports...

Posted Date: 25 Jan 2026

MTS Silicon Design Engineer

your career. Job Role and Responsibility: AMD, Inc. is hiring an MTS Silicon Design Engineer to Research, design, develop... of electronic theory. Oversee definition, design, verification, and/or documentation for ASIC development. Determine architecture...

Posted Date: 24 Jan 2026

Senior Digital Design Engineer

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role... micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Jan 2026

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP... expert, able to traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Camera Design Engineer

Summary: The Multimedia Camera HW team is looking for strong ASIC design engineer for an exciting opportunity to be involved... Domain Crossing checks, Synthesis, Timing analysis, Low power checks(CLP) Preferred Qualifications: Experience...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 07 Jan 2026

Senior Signal and Power Integrity Engineer - Hardware

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two... to optimize package, PCB, ASIC, mixed signal circuit What we need to see: BS/MS-Electrical Engineering or equivalent...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Nov 2025

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering is the center hub..., that is predominantly 3rd party IP. What You Can Expect Looking for a talented Principal Technical IP Engineer to join the Marvell Team...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year

Senior Principal Digital IC Design Engineer

Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development... experience in developing, implementing, and testing high-performance communications ASIC products. Extensive experience in RTL...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Nov 2025

Digital IC design Engineer

Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art..., place and route, and timing signoff. Collaborate with the verification team on pre-silicon verification tasks...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... and maintain automated build and regression systems for integration. • Design Constraints: Define and validate synthesis and timing...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $126800 - 190900 per year

SMTS Silicon Design Engineer

of electronic theory. Lead definition, design, verification, and/or documentation for ASIC development. Determine architecture... designs to synthesis, place and route, and timing and power use. Work with cross-functional teams including engineers...

Posted Date: 25 Jan 2026

Applied Machine Learning Engineer - VLSI Design

process variation analysis, VLSI circuit design and timing etc. Responsible for translating the requirements into a data...) 5+ years experience in circuit design, VLSI, ASIC, EDA, Silicon analysis is required Prior experience in Applied Math...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Applied Machine Learning Engineer, Circuit Design - New College Grad 2026

and timing etc. Responsible for translating the requirements into a data science problem, architect and build solutions... in Electrical/Computer Engineering (or equivalent experience). Experience with VLSI, Circuit Design, CMOS Device Physics, Timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026
Salary: $116000 - 189750 per year

AI ML Engineer, RTL Power Optimization – New College Grad 2026

, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis..., and how RTL decisions impact post‑layout power and timing. Familiarity with RTL implementation of low‑power techniques (e.g...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026
Salary: $116000 - 189750 per year

SMTS Systems Design Engineer

(software, hardware, automation, and lab setup). Lead definition, design, verification, and/or documentation for ASIC... all aspects of the process flow from high-level designs to synthesis, place and route, and timing and power use. Drive projects...

Posted Date: 24 Jan 2026

Design Engineer - Sensors

with test vectors ASIC synthesis, static timing analysis and other post-RTL tools needed for delivering timing-closed designs... devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

Senior Principal Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025