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Keywords: Board Level Test Engineer, Location: Santa Clara, CA

Page: 2

Senior Principal SERDES Engineer - Signal Integrity

candidate will have expertise in signal integrity, board-level knowledge, SERDES architecture and measurement methods... and validation. Strong knowledge of signal integrity principles, channel modeling, and board-level design for high-speed interfaces...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 11 Dec 2025
Salary: $164650 - 246700 per year

Undergrad Hardware Engineer - Oracle Cloud Infrastructure (OCI)

built specifically for the enterprise. The Hardware Engineer team works closely to define, design and integrate the... next generation of Oracle's Cloud servers and systems. As a Hardware Validation Engineer, you will gain expertise using advanced high...

Company: Oracle
Location: Santa Clara, CA
Posted Date: 28 Nov 2025

FPGA Design Engineer

board-level interfaces such as DDR, high-speed IOs, I2C, UART, SPI. Work closely with hardware engineers on schematics... buffers, DDR and high-speed IO. Good knowledge of digital electronics, schematics, and board-level design...

Location: Santa Clara, CA
Posted Date: 28 Nov 2025
Salary: $124000 - 171000 per year

Product Development Engineer FA

Engineer with a strong foundation in electrical engineering and system-level testing. This role involves working closely.... Collaborate with cross-functional teams to support board and system-level electrical design validation. Apply EE fundamentals...

Posted Date: 07 Nov 2025
Salary: $130000 per year

System Application Engineer – Data Center GPU Platforms

your career. THE ROLE: Join AMD’s Datacenter GPU Platform Application Engineering team as a System Application Engineer... bring-up and validation of AMD Instinct™ GPUs in their system, guide partners on use of AMD tools, qualification test...

Posted Date: 06 Nov 2025

Senior Silicon Product Definition Engineer

engineer for NVIDIA's family of chips and products. Architect crucial next-generation product features vital for performance.... Design tools to automate product definitions, binning, data collection, test case execution, and results analysis. Build...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

Sr. Principal Signal Integrity Electrical Engineer

to add a Principal Signal Integrity Electrical Engineer to work with our SI, electrical, mechanical, and power teams in Santa Clara... and further enhance your expertise in the field of Signal Integrity using world class SI tools and test equipment. Build...

Company: Oracle
Location: Santa Clara, CA
Posted Date: 31 Oct 2025

High-Speed Signal Integrity & Power Integrity Validation Engineer

board- and system-level SI/PI issues, performing detailed root cause analysis and recommending mitigations PREFERRED... test and measurement tools, collaborating closely with silicon design, packaging, and platform teams to ensure exceptional...

Posted Date: 31 Oct 2025

Senior FPGA Design Engineer

Vivado tools Conduct board-level bring-up and system integration testing Debug complex hardware/firmware issues using logic... analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements...

Posted Date: 07 Jan 2026

Senior Silicon Circuits System Design Engineer

across multiple business units, converting chip and board level dI/dt analysis/mitigation techniques and board PDN design knowledge.... A background in board PDN design and in-depth knowledge of chip—and board-level dI/dt analysis/mitigation techniques are helpful...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Senior Hardware Signal & Power Integrity Engineer

- Perform system level signal integrity simulations of high-speed interfaces, create simulation models and develop... channel simulation models and correlate to test structures. - Support stackup creation, develop layout/SI checklists, work...

Company: Microsoft
Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Engineer - Cloud & Infra Management

at BIOSFirmware level oFamiliar with scripting Python Shell etc oAbility to make minor changes to test automation scripts...Job Description: Role Platform Support Technician System Board Support Technician Location Santa Clara California...

Company: LTIMindtree
Location: Santa Clara, CA
Posted Date: 05 Dec 2025

ATE Hardware Engineer

to do their best work. ATE/SLT hardware team provides the interface hardware of IC package testing at final test and system level test.... What you’ll be doing: Review and approve the design of test socket, thermal plunger, and other accessories related to ATE/SLT IC...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 16 Nov 2025

Senior Staff FPGA/Firmware Design Engineer

Engineering hardware, FPGA and firmware development for on-board subsystems to support chip test infrastructure.... You will participate in hardware board development, lab testing and chip level bring up activities. Central Engineering is the center hub...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $121400 - 181800 per year

Senior Principal Hardware Engineer

. You will play a critical role in defining system architecture, guiding board-level design, and ensuring signal integrity... and performance across complex hardware systems. Architect and design high-performance board-level systems for compute, networking...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $164650 - 246700 per year

Senior Silicon Circuits System Design Engineer

across multiple business units, converting chip and board level dI/dt analysis/mitigation techniques and board PDN design knowledge... of chip—and board-level dI/dt analysis/mitigation techniques are helpful. Hands-on experience with silicon bringup...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

Analog-Mixed Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock... designs is a significant plus. Need to work closely with system and test engineers to develop high speed interface, package...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 05 Nov 2025
Salary: $105000 - 135000 per year

Senior Memory Post Silicon Qualification Engineer

, perform root-cause analysis, and drive closure of the issues found. Coordinate with design, arch, and board teams..., where required. Collaborate with the pre-Si team to understand the new features and create appropriate validation test plans. What we need...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Oct 2025

Analog-Mixed Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock... designs is a significant plus. Need to work closely with system and test engineers to develop high speed interface, package...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 22 Oct 2025
Salary: $105000 - 135000 per year