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Keywords: Board level Test Engineer, Location: Santa Clara, CA

Page: 3

Analog-Mixed Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock... designs is a significant plus. Need to work closely with system and test engineers to develop high speed interface, package...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 05 Nov 2025
Salary: $105000 - 135000 per year

Senior Memory Post Silicon Qualification Engineer

, perform root-cause analysis, and drive closure of the issues found. Coordinate with design, arch, and board teams..., where required. Collaborate with the pre-Si team to understand the new features and create appropriate validation test plans. What we need...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Oct 2025

Analog-Mixed Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock... designs is a significant plus. Need to work closely with system and test engineers to develop high speed interface, package...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 21 Oct 2025
Salary: $105000 - 135000 per year

Hardware Engineer Intern - Master's Degree

evaluations, including schematic and layout reviews Support lab activities such as board-level bring-up, testing... and professional test reports for internal and customer use Collaborate with cross-functional teams to adapt and integrate tools...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 19 Oct 2025
Salary: $27 - 53 per hour

Senior Staff Application Engineer

a tangible impact in the field of data storage. What You Can Expect Innovate, program, and execute system-level tests... and design teams to develop system-level models for evaluating next-generation technologies. Gain a comprehensive understanding...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 21 Sep 2025
Salary: $121400 - 181800 per year

Application Engineer Intern - Master's Degree

with BU and customers (if needed) about IP usage, risk assessment and IP/package/test board/test plan review, etc. in pre-silicon phases... best engineering resources for SoC bring-up and issue debug. Understand Marvell PHY/analog IPs as well as application level knowledge...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Sep 2025
Salary: $31 - 63 per hour

Principal Hardware GPU/AI Developer

Infrastructure development, is seeking a highly driven GPU Platform Hardware Engineer at the Senior Engineer level. The GPU Hardware.... Including reviews of design plans, schematics, board layout, test feature definition / guidance for subsystem test, as well...

Company: Oracle
Location: Santa Clara, CA
Posted Date: 02 Oct 2025
Salary: $96800 - 223400 per year

Sr Hardware Developer, GPU/AI and Compute

Infrastructure development, is seeking a highly driven GPU Platform Hardware Engineer at the Senior Engineer level. The GPU Hardware.... Including reviews of design plans, schematics, board layout, test feature definition / guidance for subsystem test, as well...

Company: Oracle
Location: Santa Clara, CA
Posted Date: 02 Oct 2025
Salary: $87000 - 178100 per year