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Keywords: CAD Engineer - Timing for Gate-Level Flows , Location: Sunnyvale, CA

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CAD Engineer - Timing for Gate-Level Flows & Methodologies

, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand... timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 10 Apr 2025

CAD Engineer - Timing for Gate-Level Flows & Methodologies

, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand... and Tcl or other high level programming languages Proven track record of development and deployment of complex CAD flows...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 10 Apr 2025