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Keywords: Cadence Design Systems, Location: San Jose, CA

Page: 3

FPGA/ASIC Engineer

-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA... components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 18 Sep 2025
Salary: $60 - 65.33 per hour

Senior Front End Engineer

. Exposure to design systems and component libraries (Storybook, Material UI, etc.). Experience working in Agile or Scrum teams... Responsibilities: Delivers complete solutions spanning all phases of the Software Development Lifecycle (SDLC) (design...

Company: PayPal
Location: San Jose, CA
Posted Date: 11 Sep 2025

Staff Engineer, PCB Layout

relationships with key vendors. Research new system ideas, create design plans, and modify existing systems to meet both customer... in Cadence Allegro (versions 16.x & 17.x) and experienced with high-density PCBs (up to 28 layers) and high-speed layout design...

Company: Celestica
Location: San Jose, CA
Posted Date: 23 Aug 2025
Salary: $128000 - 200000 per year

RF Module Engineer - Summer/Fall Co-Op

with marketing and systems engineering team to translate customer specifications into design requirements at the multi-chip module... in Silicon Valley amongst major customers, the Skyworks San Jose Design Center is seeking motivated individuals eager...

Company: Skyworks
Location: San Jose, CA
Posted Date: 17 Aug 2025

RF Module Engineer - Summer/Fall Co-Op

with marketing and systems engineering team to translate customer specifications into design requirements at the multi-chip module... in Silicon Valley amongst major customers, the Skyworks San Jose Design Center is seeking motivated individuals eager...

Company: Skyworks
Location: San Jose, CA
Posted Date: 16 Aug 2025

Senior Electrical PCIe Engineer

Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe... tuning to DMA/transaction layer efficiency. Ensure devices interoperate with other PCIe-compliant systems. Ensure compliance...

Company: Micron
Location: San Jose, CA
Posted Date: 16 Aug 2025

Data Lifecycle Management (DLM) Governance Specialist - USDS

global framework, conduct GAP analysis, design and implement USDS DLM-governance capabilities, including defining... verification methodologies, reporting mechanisms, and a regular cadence for data sampling and auditing. - Conduct DLM-governance...

Company: TikTok
Location: San Jose, CA
Posted Date: 09 Aug 2025

Senior Lifecycle Marketing Manager, Global Planning, Insights and Operations

artists to global brands—everything they need to design and deliver exceptional digital experiences! We’re passionate... & narrative, end of quarter reports through ongoing cadence of connection points and deliverables throughout quarter. Identify...

Company: Adobe
Location: San Jose, CA
Posted Date: 06 Aug 2025