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Keywords: Chip-Level Design Verification Engineer, Location: San Diego, CA

Page: 2

Design Methodology Engineer

Summary: Qualcomm's Design Technology team is seeking a motivated engineer to drive development of advanced methodologies... in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 20 Sep 2025

ASIC Modem Design Engineer, Project Kuiper

at Amazon! We're hiring a Modem Design Engineer within a high performance ASIC design team. This team is using industry... specification to RTL to optimizing timing / power to chip level validation. · Develop solutions optimizing customer experience...

Company: Amazon
Location: San Diego, CA
Posted Date: 12 Sep 2025

Lead Graphics Design Engineer, Shader Core

_ THE ROLE: The AMD GPU team is looking for inquisitive, motivated Lead Graphics Design Engineer, Shader Core... engineers, verification engineers, and physical design engineers teams to accomplish your tasks THE PERSON...

Posted Date: 12 Sep 2025

Principal Analog Design Engineer - Sensing Applications

Principle Analog Design Engineer is responsible for designing, simulating and validating a variety of analog functions... such as ADCs, references, charge pumps, oscillators, pads, etc. Ahead of detailed design, the Principle Analog Design Engineer...

Company: Semtech
Location: San Diego, CA
Posted Date: 10 Sep 2025
Salary: $140000 - 190000 per year

ASIC Design Engineer (Hardware Security)

sets and is seeking Hardware Design engineers with solid ASIC design experience in San Diego, CA. This is a high-level... preferred. Keywords: SoC (system on chip), Security, ASIC, Digital Design, Crypto, Cryptography, Encryption, side-channel...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 17 Oct 2025

Low Power Design/Methodology Engineer

Summary: Job Overview: Design adaptive power management controller, on-chip sensor controller and digital power meter..., and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 23 Sep 2025

Low Power Design/Methodology Engineer

Summary: Job Overview: Design adaptive power management controller, on-chip sensor controller and digital power meter..., and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 23 Aug 2025

Digital RF Systems Engineer, DBF Platform SW

inter-disciplinary teams such as ASIC/RFIC designers, FW/SW engineers, design verification engineers. You will support... . Develop detailed test plans and test procedures for pre-silicon, help with design verification as well as post silicon...

Company: Amazon
Location: San Diego, CA
Posted Date: 17 Oct 2025

Post-Silicon Structural Validation Engineer

for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement... and programming languages. 6+ months of experience with design verification methods. Minimum Qualifications: • Bachelor's degree...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 17 Oct 2025
Salary: $115600 - 173400 per year

Staff Engineer - Core Platform Bootloader

motivated engineer, a team player who is passionate tolearnnew technologies and write low level firmware that drives hardware... and firmware technology teams, besides product verification, system, architecture, tools and test teams, to instrument the firmware...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 16 Oct 2025

Power Integrity Engineer

trends and trade-offs, and chip supply design including low-power design methodologies. Deep understanding of Voltage... Engineer to join our team in Hardware Technology Group. In this role, you will be responsible for the development...

Company: Apple
Location: San Diego, CA
Posted Date: 16 Oct 2025

Senior Timing Closure Engineer - STA / Signoff - Remote

across block- and chip-level designs using Cadence Tempus for GF 22nm. Leads STA strategy for setup, hold, and OCV across corners...: U.S. Citizens or Green Card holders. Senior Timing Closure Engineer - STA / Signoff Description: Drives timing convergence...

Company: Encore Semi
Location: San Diego, CA
Posted Date: 04 Oct 2025
Salary: $140000 - 160000 per year

Senior Timing Closure Engineer – STA / Signoff - Remote

across block- and chip-level designs using Cadence Tempus for GF 22nm. Leads STA strategy for setup, hold, and OCV across corners...: U.S. Citizens or Green Card holders. Senior Timing Closure Engineer – STA / Signoff Description: Drives timing convergence...

Company: Encore Semi
Location: San Diego, CA
Posted Date: 04 Oct 2025
Salary: $140000 - 160000 per year

Timing & Synthesis Engineer

. Support digital chip integration work and flows (e.g. CDC). Collaborate with Chip Architecture, Design Verification, Physical.../Analog, Systems/PHY/MAC, RTL design/integration, Emulation, Verification, DFT, Validation, and FW/SW engineering...

Company: Apple
Location: San Diego, CA
Posted Date: 02 Oct 2025

Sr. DSP and Wireless Systems Engineer, Digital RF Systems

inter-disciplinary teams such as ASIC/RFIC designers, FW/SW engineers, design verification engineers. You will drive key..., help with design verification as well as post silicon validation, integration and characterization of RF Wireless SOC...

Company: Amazon
Location: San Diego, CA
Posted Date: 19 Sep 2025