;2G) design with complex I/O clocking. THE PERSON: As a senior member of the team, you will be working with a diverse... team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical...
/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed ( 2G) design... design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical implementation of IP through...
Execute front-end integration flows (synthesis, LINT, DFT, etc.) and generate high-quality netlists Collaborate with RTL... Strong background in ASIC or FPGA projects Proficiency in Verilog design Familiarity with front-end EDA tools and flows Advanced...
and synthesis for selected system IP components Deliver high-performance, low-power design implementations Execute front-end... projects Proficiency in Verilog design Familiarity with front-end EDA tools and flows Advanced scripting/programming skills...