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Keywords: FPGA / RTL Design Engineer, Location: San Jose, CA

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Senior Staff Emulation Engineer - ZEBU

, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include... solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2026

Senior Staff Emulation Engineer - ZEBU

, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up... services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design...

Company: Prodapt
Location: San Jose, CA
Posted Date: 13 Jan 2026

Silicon Validation Engineer 4

in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs... Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the...

Location: San Jose, CA
Posted Date: 23 Dec 2025
Salary: $144000 - 180000 per year

Embedded Adaptive Hardware Engineer

Design Engineer Location: San Jose, CA (Hybrid) Time Type: Full time Job Type: Regular Hiring Manager: Fang-Li Yuan... architecture, specifications, user guides, and design process Upgrading eFPGA architecture and RTL for the advanced features...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 09 Nov 2025

Sr. Staff Software Development Engineer

will join a team designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design... - Programming skills (C++ and Python) - Hands-on experience in RTL design and digital design, testbench development, logic...

Location: San Jose, CA
Posted Date: 18 Dec 2025

Sr. Staff Software Development Engineer

designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design...++ and Python) - Hands-on experience in RTL design and digital design, testbench development, logic verification, timing closure...

Location: San Jose, CA
Posted Date: 17 Dec 2025
Salary: $193000 - 242000 per year

Senior System Power Architect

Engineer is responsible for the design and analysis of low-power hardware and software systems. This includes low-power FPGA..., GPU, DSP, TPU) Knowledge of RTL code such as VHDL or Verilog and FPGA implementation flow (RTL, synthesis, P&R, timing...

Location: San Jose, CA
Posted Date: 21 Dec 2025
Salary: $175000 - 219000 per year