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Keywords: Lead RTL Engineer, Location: Bangalore, Karnataka

Page: 4

Serdes PHY Analog Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY...

Company: Qualcomm
Posted Date: 03 Sep 2025

High Performance DSP core Implementation Engineer, Staff

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical..., connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems...

Company: Qualcomm
Posted Date: 24 Aug 2025

FPGA Design Verification Engineer

Job Description: UST Job Title: Technical Lead II - VLSI Who we are: At UST, we help the world... FPGA Verification Engineer to join our dynamic team, working on state-of-the-art technologies. In this role...

Company: UST
Posted Date: 21 Aug 2025

Principal Digital Design Engineer

in India and seeking a Principal Digital IC Design Engineer to lead the development of advanced digital subsystems..., and RTL-to-GDS flows Excellent communication and documentation skills with strong stakeholder management Preferred Skills...

Company: onsemi
Posted Date: 08 Aug 2025

ASIC Design Engineer

of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers... architecture and high-level product requirements. Convert Chip Spec into RTL using internal IPs and external IPs. Review...

Company: Amazon
Posted Date: 01 Aug 2025

Staff Engineer, Design Verification Engineering

and sign-off criteria Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal... Engineer About the Role As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership...

Posted Date: 31 Jul 2025

Staff Engineer, Design Verification Engineering

and sign-off criteria Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal... Engineer About the Role As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership...

Posted Date: 31 Jul 2025

Staff Engineer, Design Verification Engineering

and sign-off criteria Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal... Engineer About the Role As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership...

Posted Date: 31 Jul 2025

Physical Design Engineer

Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS...+ years of experience in physical design using industry EDA tools. Lead Sub System/SOC physical design for at least 1 product...

Company: Intel
Posted Date: 19 Oct 2025

Hardware Engineer || FPGA/Design Verifcation,UVM,UMM || Exp - 7 to 11 Years

goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote... teams based in US and Italy. Your Impact Lead and mentor a team of verification engineers, driving the development...

Company: Cisco Systems
Posted Date: 15 Oct 2025

Senior Staff Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... at Marvell. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL/Analog...

Company: Marvell
Posted Date: 15 Oct 2025

Physical Design Staff Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... and complex logic blocks. Develop and implement timing and logic ECOs, collaborating closely with the RTL design team to drive...

Company: Marvell
Posted Date: 18 Sep 2025

Staff Software Engineer

experiences that consumers love. Responsibilities: Lead architecture and delivery of high-performance React/Next.js apps (SSR/ISR.... Architect scalable AEM (headless/hybrid) integrations for personalized, content-rich experiences. Mentor engineers, lead design...

Posted Date: 17 Sep 2025

Design Verification Principal Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE..., etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. - Conduct reviews...

Company: Marvell
Posted Date: 06 Sep 2025

Senior Staff Engineer-PD

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive...

Company: Marvell
Posted Date: 30 Aug 2025

Design Verification Principal Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE... VIP’s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate...

Company: Marvell
Posted Date: 27 Aug 2025

Senior Staff Engineer- Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise.... You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team...

Company: Marvell
Posted Date: 16 Aug 2025

Senior Principal Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Compute and Custom Solutions.... What You Can Expect Design, develop, implement, verify, and document micro-architecture and RTL for complex designs in the...

Company: Marvell
Posted Date: 15 Aug 2025

Staff DFT Engineer

autonomous devices like vehicles and robots to make more intelligent and safe decisions. Role Overview As a DFT Lead.... Collaborating with RTL Design, Physical Design teams and ASIC vendors to ensure proper test implementation for automotive grade SoC...

Company: Aeva
Posted Date: 31 Jul 2025

Design Principal Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE... a specification using RTL coding techniques and best practices Work with third party vendors to define customization requirements...

Company: Marvell
Posted Date: 31 Jul 2025