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Keywords: Principal CPU Systems Debug Architecture/RTL Engineer, Location: Santa Clara, CA

Page: 1

Principal Interconnect Micro-architect and RTL Design Engineer

and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team...-architecture requirements, drive technical specifications for Data Fabric IP to meet those requirements, and drive RTL execution...

Posted Date: 17 Dec 2025