. Job Description Position Overview: We are seeking a highly skilled and experienced Principal Engineer for our Static Timing Analysis (STA... with IP & Design team for Timing constraints Development & Review activities. - Develop and implement advanced STA...
Design and develop RTL in Central Engineering team for products which includes blocks such as wakeup sequencing... teams to test, debug and root-cause RTL simulation/Silicon/FPGA failures. RTL development experience Good knowledge...