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Keywords: RTL Design(DSP)-Sr, Location: Bangalore, Karnataka

Page: 2

SoC STA/Timing Engineer (Lead/Staff)

Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 13 Jun 2025

SoC STA/Timing Engineer - Staff/Senior Staff

environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 11 Jun 2025

Senior Engineer - AMS DV

year to 6 years in Design Verification Responsible for RTL and GLS level validation at SOC. Post Silicon validation... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 08 Jun 2025

Network Packet Processing Core DV

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch...

Company: Qualcomm
Posted Date: 24 May 2025

STA/Timing Methodology Engineer (Senior/Lead/Staff)

TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 22 May 2025

Technical Director, ASIC Architecture

with cross functional teams including Marketing, DSP, RFIC, SW, DFT, PD, Ops, CAD, Program Management teams Manage design..., implementation risks RTL design skills using Verilog, System Verilog or VHDL Subsystem and Chip level verification, validation...

Company: MaxLinear
Posted Date: 04 May 2025

AI/ML CAD Principal Engineer

organization. Develop and implement advanced CAD flows and methodologies for front end RTL Design to Verification Methodologies... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 17 Apr 2025

Principal Electrical Engineer

design in an HDL synthesis environment Ability to develop RTL code and understand how RTL will map to gate-level structures... through RTL design, verification, synthesis, timing closure, P&R preparation and scan insertion Experience with Verilog...

Company: Skyworks
Posted Date: 22 Mar 2025