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Keywords: RTL Design Engineer, Location: San Jose, CA

Page: 3

Post-Silicon Validation Engineer

debug. Diagnose complex silicon issues across RTL, firmware, and hardware layers. Collaborate with design, verification...Post-Silicon Validation Engineer About Etched Etched is building AI chips that are hard-coded for individual model...

Company: Etched
Location: San Jose, CA
Posted Date: 11 Oct 2025

STA Engineer

) Strong understanding of ASIC design flows, including RTL and place-and-route. Excellent problem-solving skills and attention to detail...Broadcom is looking for a senior level STA engineer. In this highly visible role, you will be contributing to highly...

Company: Broadcom
Location: San Jose, CA
Posted Date: 09 Oct 2025
Salary: $120000 - 192000 per year

ASIC Engineer Sr Staff

Design-for-Test (DFT) Engineer to join our team and contribute to the development of advanced 3nm and beyond networking... with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features. Develop and validate...

Posted Date: 08 Oct 2025

Strategic Sourcing Engineer, Silicon

). Strong knowledge of SoC design flow including RTL, synthesis, place-and-route, timing analysis, and verification. Experience dealing... fast. Strategic Sourcing Engineer, Silicon Mission: focus on the evaluation and technical support of EDA, chiplets...

Company: Groq
Location: San Jose, CA
Posted Date: 25 Sep 2025

Chip Integration Engineer

successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network.... 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Nov 2025
Salary: $120000 - 192000 per year

Verification Engineer

of industry standard verification methodologies and tools Hands on and In-depth knowledge in UVM, System Verilog, RTL design...

Company: Broadcom
Location: San Jose, CA
Posted Date: 31 Oct 2025
Salary: $120000 - 192000 per year

ASIC Engineer 2

Design size/timing/power optimization via micro-architecture/RTL/Synthesis Qualifications: Masters degree desired... mixed-signal ASICs Responsibilities: Work with system architect to define micro-architecture and RTL development...

Company: Nokia
Location: San Jose, CA
Posted Date: 24 Sep 2025

FPGA/ASIC Engineer

methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 18 Sep 2025
Salary: $60 - 65.33 per hour

Senior Custom ASIC Engineering Lead

, microarchitecture, Verilog RTL coding Front-end logic design verification, DRC, logic synthesis Knowledge of DFT methods including scan...Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas...

Company: Broadcom
Location: San Jose, CA
Posted Date: 07 Nov 2025