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Keywords: RTL Design Engineer, Location: San Jose, CA

Page: 3

Silicon Design Engineer

requires education or experience in the following: 1.Logic and circuit design; 2.RTL design or coding; 3.Verilog... your career. Job Role and Responsibility: Xilinx, Inc., a subsidiary of AMD, Inc., is hiring Silicon Design Engineers...

Posted Date: 25 Jan 2026

MTS Silicon Design Engineer

to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip... your career. Job Role and Responsibility: Xilinx, Inc., a subsidiary of AMD, Inc., is hiring MTS Silicon Design Engineers...

Posted Date: 24 Jan 2026

R&D ENGINEER IC DESIGN

/s to hundreds of Gb/s as well as various line interfaces and protocols. You will be responsible for the micro-architecture, design..., RTL coding, debugging and synthesis of complex functional blocks in the Traffic Manager / Memory Management Unit used...

Company: Broadcom
Location: San Jose, CA
Posted Date: 17 Jan 2026
Salary: $120000 - 192000 per year

Digital Design Engineer - New College Grad

an exceptional MTS Digitan Design Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working... an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities: Work with analog/digital design team...

Company: Rambus
Location: San Jose, CA
Posted Date: 23 Nov 2025
Salary: $93000 - 172000 per year

Physical Design Engineer

Perform physical design of 2nm/3nm/5nm mutli-GHz IP for network switch products. Be able to come up with floorplan..., powerplan, cts and routing of the design using state-of-art EDA tools like Innovus. Work closely with designers and must be able...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Nov 2025
Salary: $120000 - 192000 per year

SerDes Applications Design Engineer

RESPONSIBILITIES: Excellent working knowledge of RTL-based design flows Strong knowledge of firmware and hardware interaction... as well as collaboratively with engineers across a variety of AMD design, verification, and validation teams. KEY...

Posted Date: 08 Nov 2025

Design Verification Engineering (GPU)

GPU Design Verification Engineer Contract (6 months) - W2 Onsite - San Jose CA 95134 As a GPU Design Verification... Engineer, you will play a pivotal role in ensuring the quality and reliability of our GPU architecture. Creativity is essential...

Company: ConSol Partners
Location: San Jose, CA
Posted Date: 16 Jan 2026

Sr. Principal Software Engineer, Synthesis

. Job Description Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence...’s Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The...

Posted Date: 28 Jan 2026

Sr Principal Product Engineer – Memory IP

. About Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise.... We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Our customers...

Posted Date: 22 Nov 2025

Lead Application Engineer

in-depth technical assistance in collaboration with R&D to help support advanced verification flows to secure design wins..., Engineering, or related field Strong RTL and Testbench debug skills Experience in synthesizable coding style Experience...

Posted Date: 05 Dec 2025
Salary: $102900 - 191100 per year

ASIC Engineer

chips. You will also design RTL as per the architecture specs. Your collaboration with architects, and software teams... Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop...

Company: Splunk
Location: San Jose, CA
Posted Date: 26 Jan 2026
Salary: $135800 - 193400 per year

Senior Staff Emulation Engineer - ZEBU

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2026

Senior Staff Emulation Engineer - ZEBU

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 13 Jan 2026

Digital Signal Processing Engineer

Broadcom is looking for a digital signal processing engineer. In this highly visible role, you will be designing... signal processing design for SerDes and serial link high-speed data center networking. Deep understanding of DSP based...

Company: Broadcom
Location: San Jose, CA
Posted Date: 24 Dec 2025
Salary: $120000 - 192000 per year

Silicon Validation Engineer 4

Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the... in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs...

Location: San Jose, CA
Posted Date: 23 Dec 2025
Salary: $144000 - 180000 per year

Staff Engineer Digital Signal Processing

Automotive Ethernet/SerDes research and development with Design and simulation Provide the DSP spec and RTL validation support...'s technology. As a Staff Engineer Digital Signal Processing on our Research & Development team, you'll have the opportunity...

Company: Infineon
Location: San Jose, CA
Posted Date: 11 Dec 2025

Embedded Adaptive Hardware Engineer

Design Engineer Location: San Jose, CA (Hybrid) Time Type: Full time Job Type: Regular Hiring Manager: Fang-Li Yuan... architecture, specifications, user guides, and design process Upgrading eFPGA architecture and RTL for the advanced features...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 09 Nov 2025

Sr. Staff Software Development Engineer

++ and Python) - Hands-on experience in RTL design and digital design, testbench development, logic verification, timing closure... designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design...

Location: San Jose, CA
Posted Date: 21 Jan 2026
Salary: $193000 - 242000 per year

FPGA HW/SW Codesign Engineer

new features to be developed RTL Development: Design, verify, and validate high-performance logic using System Verilog...-on experience with FPGAs RTL Expertise: Expert in SystemVerilog/Verilog, synchronous design, and timing closure for high-speed...

Posted Date: 07 Jan 2026

Sr. Staff Software Development Engineer

- Programming skills (C++ and Python) - Hands-on experience in RTL design and digital design, testbench development, logic... will join a team designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design...

Location: San Jose, CA
Posted Date: 18 Dec 2025