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Keywords: RTL Design Lead - IP Design, Location: Bangalore, Karnataka

Page: 3

ARM CPU Hardening Lead

– SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores... physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing...

Company: Quest Global
Posted Date: 03 Jun 2025

Technical Lead I - VLSI

Backend or Analog design with minimal supervision Outcomes: * Work as an individual contributor owning any one task of RTL... Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture...

Company: UST
Posted Date: 14 Aug 2025

Technical Lead I - VLSI

Backend or Analog design with minimal supervision Outcomes: * Work as an individual contributor owning any one task of RTL... Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture...

Company: UST
Posted Date: 03 Aug 2025

Technical Lead II - VLSI

contributor take ownership for any one or more task/module of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout... PT/Tempus Calibre etc. (experience with one or more tools) Technical Knowledge:a. Implement IP Spec Architecture Design...

Company: UST
Posted Date: 03 Aug 2025

Technical Lead I - VLSI

Backend or Analog design with minimal supervision Outcomes: * Work as an individual contributor owning any one task of RTL... Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture...

Company: UST
Posted Date: 03 Aug 2025

Technical Lead II - VLSI

contributor take ownership for any one or more task/module of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout... PT/Tempus Calibre etc. (experience with one or more tools) Technical Knowledge:a. Implement IP Spec Architecture Design...

Company: UST
Posted Date: 03 Aug 2025

Senior Staff Engineer-PD

role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise...

Company: Marvell
Posted Date: 31 Aug 2025

Senior DFT Engineer

verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including:  Drive.... Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning...

Company: Amazon
Posted Date: 30 Aug 2025

Senior DFT Engineer

verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including:  Drive.... Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning...

Company: Amazon
Posted Date: 30 Aug 2025

Senior Technologist, ASIC Development Engineering

. SanDisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting...: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware...

Company: SanDisk
Posted Date: 26 Aug 2025

Principal Engineer, STA

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As member of the Physical Design team... at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity...

Company: Marvell
Posted Date: 22 Aug 2025

Associate II - VLSI SC Char

of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...

Company: UST
Posted Date: 15 Aug 2025

Associate III - VLSI SRAM ACD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 15 Aug 2025

Associate III - VLSI Analog Layout

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 15 Aug 2025

Associate III - VLSI ML

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 08 Aug 2025

Associate III - VLSI IO

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 07 Aug 2025

Pre-Silicon Validation Engineer

, you will participate and lead the verification of IP, Sub-systems and SoC. You will focus on executing pre-Silicon validation plans... network technologies that currently lead and continue to transform datacenter ecosystems. As a world-class organization, we're...

Company: Intel
Posted Date: 06 Aug 2025

Associate I - VLSI

of VLSI Frontend Backend or Analog design Outcomes: * Works as an individual contributor and on any one task of RTL Design... Knowledge Examples: Basic understanding in any of the design by executing any one of – RTL Design / Verification / DFT...

Company: UST
Posted Date: 03 Aug 2025

Associate II - VLSI

of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...

Company: UST
Posted Date: 03 Aug 2025

Associate III - VLSI

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 03 Aug 2025