Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: RTL Synthesis Engineer, Location: San Jose, CA

Page: 2

ASIC Engineering Technical Leader - SDC

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... as early as possible in design cycle. Review block level SDCs and clocking diagrams and mentor other RTL design owners on SDC...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 14 Aug 2025

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 06 Jun 2025