: A successful candidate will work on full chip SoC physical integration, verification and tapeout with physical design engineers. The...: Drive Full chip physical integration and verification (DRC/LVS, ERC, DFM checks) Work with fab and fab contacts for all the...
_ SMTS SILICON DESIGN ENGINEER(Timing Constraints/STA Signoff Technical Lead) THE ROLE: As a member of the AECG ASIC... and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring...
_ SMTS SILICON DESIGN ENGINEER (AECG ASIC Physical Design & Implementation) THE ROLE: The focus of this role in the AECG..., Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR...