Senior RTL Design Engineer MUST be a US Citizen Remote / work from any US location Full-time/employee + Bonus... synthesis and static timing analysis Modeling SoC architectures with FPGAs RTL Design including HVLs and HDLs (SystemVerilog...
Senior Design Verification Engineer Remote / work from any US location US Citizen or US Permanent Resident Full-time... of junior team members. Run simulations to verify design against specifications. Analyze results, identify issues, and debug...
ASIC Design Verification Engineer US Citizen Full-Time + Health Benefits + 401K Plan with profit sharing + PTO... languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. A strong background in RTL based digital IC design using Verilog...