of digital logic design, IP/SoC architecture and microarchitecture Experience Working knowledge of Synthesis, STA, Lint & CDC...Design and develop RTL in Central Engineering team for products which includes blocks such as wakeup sequencing...
Responsibilities MaxLinear is seeking Senior Staff ASIC Verification Lead Engineer to work from our Bangalore, India... Design Centre. The ideal candidate will have an ASIC verification background with experience in SOC verification using...
General Summary: 8 to 14 years of work experience in ASIC RTL Design Experience in Logic design/micro-architecture/RTL... on experience in Low power design is required Experience in Synthesis / Understanding of timing concepts for ASIC is and added...