Develop and execute UVM-based testbenches for ASIC/SOC verification. Create and implement detailed verification plans for complex IP blocks. Design and run directed/randomized tests to validate functionality and performance. Debug fai...
Develop and validate complex multi-mode/multi-corner timing constraints (SDC) for RTL and signoff Perform pre-route timing checks and QoR cleanup to ensure smooth STA handoff Debug and resolve timing violations using Synopsys Primetime/...