. What You Can Expect Develop and maintain verification environment in UVM (Universal Verification Methodology) Define and review..., Electrical Engineering or related fields and 4 to 20 years of related professional experience. Verification experience in SV...
Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure... center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry...
_ PMTS SILICON DESIGN ENGINEER We are currently seeking a highly skilled 15+ years Performance Verification engineers... Experience with advanced verification methodologies and languages like C/C++ UVM, system Verilog. Scripting Python/Perl...