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Keywords: ASIC Timing and Methodology Engineer, Location: San Diego, CA

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ASIC Timing and Methodology Engineer

Summary: As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive.... You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in class timing ECO tools . Work on timing sign...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 23 Aug 2025

Library Characterization and Timing Methodology Engineer

analysis and visualization & large-scale software automation enablement. Excellent understanding of statistical Liberty timing... and design flows for Static Timing Analysis, Spice / Fast spice simulation, Synthesis, DFT, Power Analysis Education...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 26 Sep 2025

Cellular ASIC Methodology Engineer

! Description As a Cellular ASIC Methodology Engineer, you'll develop and optimize design and implementation methodology for integrated circuits... STA methodology improvements using industry-leading timing tools and ECO methodologies MULTI-FUNCTIONAL COLLABORATION...

Company: Apple
Location: San Diego, CA
Posted Date: 14 Sep 2025

Timing & Synthesis Engineer

areas, and thrive during critical times. Description As a Timing Engineer, you will work in a team developing Wireless... Qualifications Strong knowledge of the entire ASIC design process, from RTL through synthesis, static timing analysis and place...

Company: Apple
Location: San Diego, CA
Posted Date: 02 Oct 2025

Design Methodology Engineer

in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime... Summary: Qualcomm's Design Technology team is seeking a motivated engineer to drive development of advanced methodologies...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 20 Sep 2025

Low Power Design/Methodology Engineer

. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check... cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 24 Sep 2025

Low Power Design/Methodology Engineer

. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check... cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 22 Aug 2025

HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff

insights on timing risks and mitigation strategies. Define and implement low-power architecture using CLP methodology... Summary: We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025

HW SOC/ASIC Physical Design Engineer, Principal

insights on timing risks and mitigation strategies. Define and implement low-power architecture using CLP methodology... Summary: We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025

HW SOC/ASIC Physical Design Engineer, Senior

insights on timing risks and mitigation strategies. Define and implement low-power architecture using CLP methodology... Summary: We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 18 Oct 2025
Salary: $115600 - 173400 per year

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. The front end of the DDR controller... interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 09 Oct 2025

SoC Power/Performance Post-Si Validation & Emulation Engineer

: Strong familiarity with Static Timing Analysis and Physical Design tools & methodology. Solid understanding of circuit and logic design... Summary: As a SoC Power/Performance Post-Si Validation & Emulation Engineer, you will be a vital member of our Global SoC...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 11 Oct 2025

Design Implementation Engineer-Synthesis

Summary: The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing... all aspect of front end implementation design challenges and methodology. As a member of the Graphics team, the...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 01 Oct 2025

VLSI Design Engineer for Server / Data Center Products

is looking for bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or FPGA design experience... team responsible for RTL Design, flows and methodology for high performance ASICs in the latest process nodes for High...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 05 Sep 2025