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Keywords: Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer, Location: San Diego, CA

Page: 1

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Summary: Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team... is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. The front end of the DDR controller...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 09 Oct 2025