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Keywords: Advanced Packaging Engineer - SI/PI, Location: Santa Clara, CA

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Advanced Packaging Engineer - SI/PI

, and validation of advanced IC packages supporting high‑speed interfaces. Your work in SI/PI will directly influence product... engineering, and marketing to support package planning and substrate design. Build and correlate SI/PI models for advanced...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 21 Jan 2026
Salary: $97630 - 146300 per year

Senior Signal Integrity / Power Integrity (SI/PI) Engineer

intersection of advanced simulation, next-generation SerDes (112G/224G/448G PAM4), and innovative routing, packaging, and power... be possible without our Signal Integrity (SI) and Power Integrity (PI) engineers who design, simulate, and characterize interconnects...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 14 Dec 2025

Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects and power... architects, ASIC vendors, layout, packaging, and optical teams to co-optimize performance, manufacturability, and reliability...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 26 Nov 2025

High-Speed Signal Integrity & Power Integrity Validation Engineer

such as PCIe Gen6/7 and Ethernet 224G per lane. You will work hands-on in a world-class lab environment equipped with advanced... test and measurement tools, collaborating closely with silicon design, packaging, and platform teams to ensure exceptional...

Posted Date: 31 Oct 2025

Package Development, Signal Integrity and Power Integrity Engineer, Staff

is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic... engineer to contribute to the development of advanced microelectronic packages for semiconductors supporting 448 Gb/s data...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 17 Dec 2025
Salary: $105470 - 158000 per year

Senior Hardware Engineer

experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage..., etc. layout and able to direct layout engineer with clear design priority PI and SI tools (HFSS, ADS, Cadence) high density...

Company: Intel
Location: Santa Clara, CA
Posted Date: 26 Nov 2025

Package Development, Signal Integrity and Power Integrity Engineer, Senior Principal

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging team... copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 15 Jan 2026

Signal & Power Integrity Engineer Intern - Master's Degree

is seeking a motivated intern to support the development of advanced microelectronic packages for high-speed semiconductor...-on experience collaborating with cross-functional teams and learning about cutting-edge packaging technologies. What You Can...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 10 Dec 2025
Salary: $27 - 55 per hour