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Keywords: CAD Design Verification Methodology Engineer, Location: Cupertino, CA

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CAD Design Verification Methodology Engineer

contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts. You will work... detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance...

Company: Apple
Location: Cupertino, CA
Posted Date: 07 Aug 2025

Physical Design Methodology Engineer, Annapurna Labs

design methodology and CAD flows. - Develop cloud infrastructure to support physical design work. - Drive improvement... in developing design methodology or CAD flows in synthesis, PNR, or sign-off areas for advanced technology nodes. - Experience...

Company: Amazon
Location: Cupertino, CA
Posted Date: 27 Aug 2025

Sr. Physical Design Methodology Engineer, Annapurna Labs

technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies... physical design methodology or CAD flows in synthesis, PNR, and sign-off areas for advanced technology nodes. - Proficient...

Company: Amazon
Location: Cupertino, CA
Posted Date: 26 Jul 2025

Power UPF Methodology Engineer

-out. - Liaison with CAD and physical design verification team for debugging any power ERC and power intent flow issues... methodology for next generation mobile products, including: - Drive Mixed signal IP power ERC and power intent verification...

Company: Apple
Location: Cupertino, CA
Posted Date: 28 Jun 2025