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Keywords: CPU Design Timing Engineer, Location: Santa Clara, CA

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CPU Implementation Engineer

implementation. Description As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro... on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design • Work with x-functional top...

Company: Apple
Location: Santa Clara, CA
Posted Date: 02 Jul 2025
Salary: $126800 - 190900 per year

CPU Gate Level Synthesis Engineer

groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level... CPU design team, working in a multi-functional role to ensure that our CPUs meet the highest standards for performance...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Jun 2025

Principal CPU Systems Debug Architecture/RTL Engineer

Engineering General Summary: We are hiring a talented engineer for CPU System Debug Architecture/RTL engineer targeted... design principles along with timing and power implications. Preferred qualifications ● MS degree or Phd in Computer...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 21 Apr 2025

CPU Systems RTL Engineer

debugging tools. ● Knowledge of logic design principles along with timing and power implications. Preferred qualifications... design to target power, performance, area and timing goals. ● Functional verification support. Help the design verification...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 20 Apr 2025

Senior Logic Design Engineer, Cache Coherent Interconnects

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team..., you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 02 Jul 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade... help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Jun 2025

SoC Design Engineer

We seek a skilled front-end SoC design engineer. A customer driven professional with a track record of effective... experience in design services. 2-3 of the following: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy...

Posted Date: 01 Jun 2025

Physical Design Methodology CAD Engineer

. Understanding of some of the analysis involved in Physical Design - extraction, timing, noise, physical verification, EMIR. Pay... detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance...

Company: Apple
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

ASIC Design Engineer - New College Grad 2025

measurement, Reset and Boot controllers. You will be responsible for the RTL design, logic synthesis, and timing analysis... a more exciting time to join our team! NVIDIA is seeking outstanding ASIC Design Engineers to design and implement the world...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Jun 2025
Salary: $96000 - 184000 per year

SoC Design Engineer

timing control design and STA; Perform chip bring-up, validation and debugging; Design, integrate and validate ISP data pipes.... Required knowledge and/or skills from the graduate level course work: VLSI circuit and system design with Verilog, Static timing...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 26 Jun 2025
Salary: $151091 - 155000 per year

SoC Design Engineer

timing control design and STA. Perform chip bring-up, validation and debugging. Design, integrate and validate ISP data...Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 30 Apr 2025
Salary: $151091 - 155000 per year

Senior Reset and Boot ASIC Engineer

. You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. Integrate modules into the overall SOC... and synchronous Reset design, synthesis, timing analysis, and Spyglass/CDC/RDC checks Excellent analytical and problem-solving...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 18 Jun 2025

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... and maintain automated build and regression systems for integration. • Design Constraints: Define and validate synthesis and timing...

Company: Apple
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

Lead Speed and Reliability Engineer - DFP

a plus, related to timing, speed, reliability and power. Familiarity with STA timing closure, circuit design, noise characterization..., multi-functional team at NVIDIA. We sit at the crossroads of design, architecture, marketing and productization...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 May 2025