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Keywords: DV Engineer (PCIE), Location: Bangalore, Karnataka

Page: 1

DV Engineer (PCIE)

. Position: DV Engineer (PCIE) Location:Bangalore Work Type: Onsite Job Type: Full time Job Description: An experienced... ASIC verification engineer with a good experience and fair understanding of interface protocol PCIe Gen1/2/3/4/5/6...

Company: TekWissen
Posted Date: 07 Jun 2025

Verification Engineer, PCIE

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI...: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub...

Company: Nvidia
Posted Date: 08 Jun 2025

Senior Verification Engineer, PCIE

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation...: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub...

Company: Nvidia
Posted Date: 02 Jun 2025

Senior Verification Engineer, PCIE

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation...: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub...

Company: Nvidia
Posted Date: 31 May 2025

ASIC DV Engineer, Networking

silicon success. ASIC DV Engineer, Networking Responsibilities Define and implement IP/SoC verification plans, build...Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals...

Company: Meta
Posted Date: 24 May 2025

ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

Meta is hiring ASIC Verification Engineer with background in Simulation Acceleration using Emulation and Hybrid... and Emulation to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part...

Company: Meta
Posted Date: 23 May 2025

Serdes PHY Analog Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY...

Company: Qualcomm
Posted Date: 08 Jun 2025

ASIC SoC Verification Engineer

_ SILICON DESIGN ENGINEER 2 (AECG ASIC - SoC verification Engineer) THE ROLE: The focus of this role is to plan, build... to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams...

Posted Date: 01 Jun 2025

ASIC - SoC Design Verification Engineer

_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification) THE ROLE: The focus of this role is to plan, build... to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams...

Posted Date: 09 May 2025

FPGA Verification Engineer || Verilog/System Verilog/UVM Methodologies || Experience 8+ years

spans both sophisticated data-path and challenging control-path FPGAs. The verification process includes crafting the DV... architecture, test plan, and coverage plan, all the way through to final DV sign-off. We leverage industry-standard tools...

Company: Cisco Systems
Posted Date: 14 Jun 2025

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years

, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level... environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block...

Company: Cisco Systems
Posted Date: 29 May 2025

ASIC Design Verification Engineer | UVM | Exp- 8+ Years

, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV... environment infrastructure. Develop DV infrastructure from scratch for block, cluster and top-level environments. Maintain...

Company: Cisco Systems
Posted Date: 13 May 2025

Staff Design Verification Engineer

such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM & Formal DV Architect the testbench and develop the... such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations...

Posted Date: 11 May 2025

Senior Digital Design Engineer

of Design Verification (DV) practice, ease of integration and make recommendations Build expertise on complex interfaces..., peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D Develop and maintain...

Posted Date: 11 May 2025

Senior Digital Design Engineer

of Design Verification (DV) practice, ease of integration and make recommendations Build expertise on complex interfaces..., peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D Develop and maintain...

Posted Date: 07 May 2025

Serdes PHY Analog Design Engineer

sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.... Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added...

Company: Qualcomm
Posted Date: 10 Apr 2025

Senior Digital Design Engineer

of Design Verification (DV) practice, ease of integration and make recommendations Build expertise on complex interfaces..., peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D Develop and maintain...

Posted Date: 02 Apr 2025

VLSI Lead

3. Lead Design Verification Engineer Job Description: 7+ years of hands-on DV experience in SystemVerilog/UVM... information, visit us at www.wipro.com. Long Description 1. ASIC RTL Engineer Job Description: RTL, Coding, Design, IP...

Company: Wipro
Posted Date: 09 Jun 2025

ASIC SoC Verification Lead

_ MTS SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan... and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform...

Posted Date: 01 Jun 2025

SOC IP Verification Lead

_ SMTS SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan... and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform...

Posted Date: 01 Jun 2025