with architects and designers to understand the design intents. Creating and executing formal verification plans for design blocks... or FPGA. Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC...
with architects and designers to understand the design intents. Creating and executing formal verification plans for design blocks... or FPGA. Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC...