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Keywords: IP/ Subsystem Design Lead, Location: Bangalore, Karnataka

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IP/ Subsystem Design Lead

. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively... architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: The...

Posted Date: 25 Oct 2025

RTL Design Lead - IP Design

cutting-edge designs. You will lead a front-end design and integration team, working closely with the architecture, IP design... IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC...

Posted Date: 23 Aug 2025

IP Design Verification Lead

of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion... other subsystem applications. The person: A talented hardware/firmware co-design/verification engineer with strong records...

Posted Date: 04 Sep 2025

IP/SoC Verification Lead

you will be: Developing and executing test plans for Unit/IP/Subsystem/ SOC level verification System Verilog test bench development... your career. MTS SILICON DESIGN ENGINEER THE TEAM: AMD's NTSG - Network Technologies Solutions Group is a leading provider...

Posted Date: 11 Oct 2025

Lead Design Engineer

. Job Description Be part of the Cadence DDR PHY IP Front End Design team responsible for - Develop firmware for DDR5 PHY using... on Microcontrollers. Responsible for collaborating with hardware designers and memory subsystem architects to derive training...

Posted Date: 12 Oct 2025

Digital Design Lead

state of the art. About the Role As SOC Design Lead one will be responsible for driving complex SOC project..., Emulation and Software. Key Responsibilities SOC Design and Development Lead End to End design for complex SOCs in IOT...

Posted Date: 20 Sep 2025

DSP / NPU Senior Lead Design Verification Engineer

from chipsets and royalties from intellectual property. Job Responsibilities: · Drive design verification of DSP IP by working... environments, and meet coverage goals. · Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level...

Company: Qualcomm
Posted Date: 10 Sep 2025

Techincal Lead- Design Verification

Job Requirements The ideal candidate for this Senior Lead Verification Engineer position... should have a strong background in verification methodologies and be able to effectively lead a team in achieving project goals. 10-12 Yrs of work...

Company: Quest Global
Posted Date: 13 Aug 2025

V&V Designer

portfolio in the industry. Every day, 80,000 colleagues lead the way to greener and smarter mobility worldwide, connecting... (System, Project, Product, Quality, and Safety teams), design overall tests, and perform functional testing using advanced...

Company: Alstom
Posted Date: 30 Sep 2025

V&V Designer

portfolio in the industry. Every day, 80,000 colleagues lead the way to greener and smarter mobility worldwide, connecting... (System, Project, Product, Quality, and Safety teams), design overall tests, and perform functional testing using advanced...

Company: Alstom
Posted Date: 30 Sep 2025

Staff Digital Design Engineer

serial standards Experience with IP, subsystem-level design and integration Proficiency in scripting languages (Python, TCL... in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital...

Company: onsemi
Posted Date: 28 Sep 2025

Design Verification Senior Principal Engineer

architecture, and milestone reviews - Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan... architecture, and milestone reviews - Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan...

Company: Marvell
Posted Date: 20 Sep 2025

CPU/Core/Processor RTL Design Architect

crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC... of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design...

Posted Date: 14 Sep 2025

Design Verification Senior Staff Engineer

/Career solutions including the CXL product line. What You Can Expect Develop and maintain testbenches for IP, subsystem...–10 years of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology...

Company: Marvell
Posted Date: 06 Sep 2025

Senior Staff Engineer- Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the...

Company: Marvell
Posted Date: 16 Aug 2025

ASIC Design Engineer

architects, IP developers and physical design teams to develop SoCs that meets the power, performance and area goals for Amazon... chip level and subsystem level netlists integrating IPs and new design. Work with Chip Architects to understand...

Company: Amazon
Posted Date: 01 Aug 2025

Design Principal Engineer

performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers Implement... etc. owning full chip, subsystem and block level architecture and design Expertise in any of the following domains...

Company: Marvell
Posted Date: 31 Jul 2025

Senior Manager, Design Verification Engineering

Design Verification team at Aeva India, you will build and lead a team of talented verification engineers to verify new... and execute verification test plan for IP, Block, Subsystem, and ARM-based SOC using System Verilog/UVM methodology and C-based...

Company: Aeva
Posted Date: 30 Jul 2025

Lead I - Embedded Software

project Number of review feedback post Software Lead II review based on project SLA Number of design and test defects post...: * Lead requirement engineering; collaboration with internal and external customers to understand their needs Design...

Company: UST
Posted Date: 25 Oct 2025

Lead I - Embedded Software

project Number of review feedback post Software Lead II review based on project SLA Number of design and test defects post...: * Lead requirement engineering; collaboration with internal and external customers to understand their needs Design...

Company: UST
Posted Date: 28 Aug 2025