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Keywords: IP Logic Design Engineer, Location: Santa Clara, CA

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IP Logic Design Engineer

level (RTL) development for the IP block and implements the specification for logic components Ensures quality of design... Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance...

Company: Intel
Location: Santa Clara, CA
Posted Date: 04 Feb 2026

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

, that is predominantly 3rd party IP. What You Can Expect Looking for a talented Principal Technical IP Engineer to join the Marvell Team... into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider. Post-silicon validation...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 15 Nov 2025
Salary: $143200 - 214500 per year

MTS Silicon Design Engineer

your career. Job Role and Responsibility: AMD, Inc. is hiring an MTS Silicon Design Engineer to Research, design, develop... design, logic design, and/or system simulation. Define module interfaces/formats for simulation. Lead the development...

Posted Date: 25 Jan 2026

ASIC Design Engineer, GPU/ML Shader Core

your career. THE ROLE: We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status... of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems...

Posted Date: 19 Dec 2025

Digital IC Principal Design Engineer

Engineer at Marvell, you will be a member of the Custom Compute Solution IP development team. This team develops uniquely high... data path circuits, and high-speed DSP data path. Take ownership of design IP including updating, maintaining...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $146850 - 220000 per year

FPGA Design Engineer

an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC/MPSoC platforms and practical experience in camera... and supporting hardware bring-up for new boards. Key Responsibilities FPGA & Zynq Development Design and implement FPGA logic...

Location: Santa Clara, CA
Posted Date: 28 Nov 2025
Salary: $124000 - 171000 per year

RTL Design Engineer - Intermediate (US)

Process: Onsite / Teams based on where the candidate is. Top 3-5 Must Have Skills for this role - RTL Design - FPGA... experience in design, simulation, synthesis, implementation - Vivado Experience - TCL, Python coding JOB DUTIES...

Company: LanceSoft
Location: Santa Clara, CA
Posted Date: 04 Feb 2026

RTL Design Engineer - Intermediate

to architecture, design, and documentation for Ips. RTL Development: Design, verify, and validate high-performance logic using System..., Ethernet, and DDR5/6. System Level Integration: Utilize the client (Xilinx) Vivado and Vitis ecosystems to integrate custom IP...

Company: Cynet Systems
Location: Santa Clara, CA
Posted Date: 03 Feb 2026
Salary: $53.62 - 58.62 per hour

SMTS Systems Design Engineer

development. Determine architecture design, logic design, and/or system simulation; define module interfaces/formats... your career. Job Role and Responsibility: AMD, Inc. is hiring SMTS Systems Design Eng. to Research, design, develop, and/or test...

Posted Date: 25 Jan 2026

ASIC/RTL Design Engineer

Design. Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging...Duration: 6 months Job Duties: The work will expose the designer to a number of IP including ARM cores, Ethernet...

Location: Santa Clara, CA
Posted Date: 23 Jan 2026

SOC Design Engineer

on developing the logic design, register transfer level (RTL) coding, integration, and simulation for AI System on Chips (SoCs... implementation. Key Responsibilities Develops the logic design, register transfer level (RTL) coding, simulation, and integrates...

Company: Intel
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Design Engineer - Sensors

devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification... tools. Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

Principal Interconnect Micro-architect and RTL Design Engineer

and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team... optimization, along with power impact at architecture and logic design Excellent communication, management, and presentation...

Posted Date: 17 Dec 2025

Senior Staff Engineer, Physical Design

infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior Staff Hardware Design Engineer - PCB Board Level Circuit Design Simulation Test

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Design and architecture for Central... advanced silicon IP to be used by all the other fast growing business units including Data Center, Enterprise, Optics, Custom...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $121400 - 181800 per year

Senior Layout Mask Design Engineer

, to amplify human creativity and intelligence. We are looking for you! You'll work on the design and development... of our next generation custom SRAMs. As part of the Digital IP Team, you will work with other team members in cutting edge process...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025
Salary: $124000 - 195500 per year

Physical Design Methodology Engineer

, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve... related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams...

Posted Date: 09 Nov 2025

Senior Staff FPGA/Firmware Design Engineer

, AXI). Strong knowledge and application of high-speed design methodologies for FPGA logic. Solid understanding of digital... design principles and synchronous design techniques. Experience with Logic level interface of service processors...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

FPGA Prototyping Engineer

/HAPS platforms across AMD’s next-generation silicon programs. You will collaborate closely with architecture, RTL design..., performance studies, and system integration long before silicon availability. This role is ideal for an engineer who enjoys...

Posted Date: 04 Feb 2026

Formal Equivalence Checking Methodology Engineer

Formal Equivalence Checking Methodology Engineer to join our VLSI team. This team is responsible for developing, maintaining... is crucial in ensuring the functional equivalence of our designs throughout the design cycle, from RTL to GDSII! What you’ll...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Jan 2026