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Keywords: Interconnect RTL Design Engineer, Location: Santa Clara, CA

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Interconnect RTL Design Engineer

and synthesizable system Verilog RTL Run unit level testing to deliver quality code to the Design Verification Team Create assertions... and analytical skills Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL. Working knowledge...

Posted Date: 24 Aug 2025

Senior Design Engineer, Coherent High Speed Interconnect

NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! For two decades, NVIDIA... (MS, PhD) a plus. 5+ years or relevant design experience Knowledge of industry standard interconnect protocols...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Sep 2025

Senior IP Design Verification Engineer

corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams..., we are building a better tomorrow. Who We Are We are seeking a highly skilled Verification Engineer to work on verification...

Company: Intel
Location: Santa Clara, CA
Posted Date: 18 Sep 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade... in one or more areas of cache design, on-chip interconnect network, data compression or shader processor Ability to work well in a team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 14 Sep 2025
Salary: $126800 - 190900 per year

Senior Logic Design Engineer– Physical Design

We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design... Team, you will be responsible for the design of CPU on-chip interconnect network and last-level caches, working closely...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Sep 2025

Senior ASIC Design Engineer

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU.... A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis, ECO, and post...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jul 2025

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $126800 - 190900 per year

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... design experience in: o memory system development o RTL/micro-architecture definition o PPA (performance/power/area...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... design experience in: o memory system development o RTL/micro-architecture definition o PPA (performance/power/area...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

Senior Digital Design Engineer - High-Speed I/O and Photonics

will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Sep 2025

Senior Digital Design Engineer - High-Speed I/O and Photonics

will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Sep 2025

Advanced Device Modeling Expert - TCAD

roadmap development by evaluating new materials, interconnect structures, process flows and design. Drive design... new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers...

Location: Santa Clara, CA
Posted Date: 22 Oct 2025