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Keywords: Lead Engineer - RTL/SoC Integration, Location: Bangalore, Karnataka

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Lead Engineer - RTL/SoC Integration

Job Requirements Lead Engineer - Individual contributor who loves challenging and rewarding career in RTL design... and integration. Work Experience Required: RTL design, Verilog, SoC Integration, CDC, Lint Desirable: Basic Synth/Timing...

Company: Quest Global
Posted Date: 14 Feb 2025

SOC RTL/DFX execution Lead (SMTS Silicon Design Engineer)

_ SMTS SILICON DESIGN ENGINEER THE ROLE: Circuit Technology team is looking for a passionate and experienced test chip RTL... of SOC DFT features (TAP controller, JTAG/IJTAG, GPIOs, ESD structures etc) into RTL. Gate level simulation using Synopsys...

Posted Date: 08 May 2025

Lead Engineer - RTL/SoC

Job Requirements Individual contributor Lead engineer - RTL and SoC integration Work Experience Mandatory: RTL..., Verilog, SoC Integration, Digital Design Desiared: Basic synthesis/timing, Python scripting for automating task...

Company: Quest Global
Posted Date: 19 Feb 2025

RTL/Integration- Subsystem/IP Design Lead

design, Physical Design teams, and product engineers to achieve first pass silicon success. RTL/Integration- Design... IP/SoC team. Key Responsibilities: Design of Subsystems with integration of AMD and other 3rd party IPs Perform...

Posted Date: 23 Apr 2025

ASIC RTL Design Engineer (Display) - Sr Lead

. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL..., Microelectronics, Computer Science, or related field. 4+ years RTL Design/Hardware Engineering experience or related work experience...

Company: Qualcomm
Posted Date: 07 May 2025

Principal Engineer, RTL ASIC Design

on Full Chip Integration of Complex SoC design. Has worked on complex chips such as network processors, CPUs ,GPUs ,NOCs..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom and Compute Solutions...

Company: Marvell
Posted Date: 23 Mar 2025

ASIC Physical Design & Implementation Lead

_ SMTS SILICON DESIGN ENGINEER (AECG ASIC Physical Design & Implementation) THE ROLE: The focus of this role in the AECG... ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer...

Posted Date: 11 Apr 2025

Senior DFT Engineer

. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning... logic and components into full SoC and subsystem RTL netlists.  Review and sign-off SoC level DFT mode timing closure...

Company: Amazon
Posted Date: 08 May 2025

ASIC Design Engineer

of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers... Architecture and Design of custom IPs for integration into SOC's. Design & Develop RTL for Interfaces, Power Management, Clocking...

Company: Amazon
Posted Date: 07 May 2025

High Performance DSP core Implementation Engineer, Senior

integration and product enhancement routines Should lead implementation flow development effort independently by working... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 10 Apr 2025

High Performance DSP core Implementation Engineer, Sr Staff

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify...

Company: Qualcomm
Posted Date: 09 Apr 2025

MTS SILICON DESIGN ENGINEER

_ MTS SILICON DESIGN ENGINEER ( SOC Low Power-RTL lead) THE ROLE: As a member of the Client Group, you will help bring... simulation tools (VCS) and Clock domain crossing (CDC) tools Proficient in IP level ASIC or SoC level RTL integration work...

Posted Date: 29 Mar 2025

Physical Design (MTS Silicon Design Engineer)

_ MTS SILICON DESIGN ENGINEER THE ROLE: As the SoC Subsystem Physical Design Lead, you will lead the physical design..., and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve...

Posted Date: 20 Mar 2025

MTS Silicon Design Engineer

of RTL/SOC design/integration with Verilog/system Verilog Mentoring juniors and enhancing their skill set..._ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new...

Posted Date: 08 Feb 2025

Serdes PHY Analog Design Engineer

sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY... which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance...

Company: Qualcomm
Posted Date: 09 Apr 2025