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Keywords: Power Optimization & Analysis Engineer, Location: Santa Clara, CA

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Silicon Power Analysis and Optimization Engineer - San Jose, CA - AMDJP00004575

Position Title: Power Optimization Engineer Location: San Jose, CA (Hybrid) Clearance Requirements: None Position... Status: Contract (W2 only) Pay Rate: $90-$130/hr Position Description: We are seeking a Power Optimization Engineer...

Company: Seneca Resources
Location: Santa Clara, CA
Posted Date: 25 Sep 2025

Power Optimization & Analysis Engineer

_ THE ROLE: We are seeking a highly motivated, innovative, and dedicated engineer to join the Power Competitive Group...; we are a group that is driving advanced power attainment, power optimization and power management techniques for AMD IPs & Products...

Posted Date: 24 Aug 2025

Senior SoC Power Analysis Engineer

We are now looking for a Senior SoC Power Analysis Engineer! NVIDIA is seeking an exceptional silicon power analysis... and optimization engineer to help us build power-efficient and performance-leading SOC's. This position offers the opportunity...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Sep 2025

EDA Workflow Optimization Engineer

decades, inventing the GPU in 1999 to reshape PC gaming and modern computer graphics. As an engineer in our EDA Workflow... Optimization team, you will partner closely with our engineering teams worldwide. You will understand workflows covering the full...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Oct 2025

EDA Workflow Optimization Engineer

decades, inventing the GPU in 1999 to reshape PC gaming and modern computer graphics. As an engineer in our EDA Workflow... Optimization team, you will partner closely with our engineering teams worldwide. You will understand workflows covering the full...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Sep 2025

Sr. Staff Static Timing Analysis (STA) Engineer

Physical Design team at Marvell in Santa Clara is seeking a Sr. Staff Static Timing Analysis (STA) Engineer to contribute... our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $124420 - 186400 per year

GPU Electrical Analysis Engineer

on experience in physical design and large chip integration. Description As a GPU Electrical Analysis engineer, you will work..., and package design/optimization will be required. You will develop test structures, procedures/automation, and analysis...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Aug 2025

Signal and Power Integrity Engineer - Hardware

We are now looking for a Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two... problems. Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D EM tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Oct 2025
Salary: $108000 - 184000 per year

Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

/ Power Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects..., or similar. Experience with power delivery design, including decoupling strategies, PDN impedance analysis, and noise mitigation...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 12 Oct 2025

Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

/ Power Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects..., or similar. Experience with power delivery design, including decoupling strategies, PDN impedance analysis, and noise mitigation...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 12 Oct 2025

Server Chipset Power Engineer

involves estimation, analysis and optimization of Power, Performance and Thermal metrics of Server chipset. The ideal... of experience in low power design and optimization. Experience in design and/or analysis of low power features at SoC, chipset...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 19 Sep 2025

Senior Video ASIC Design Engineer

, functional coverage definition, synthesis, power, timing, and area optimization, static checks, and support of physical design...We are now looking for a Senior Video ASIC Design Engineer! NVIDIA has been transforming computer graphics, PC gaming...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Oct 2025

Hardware Validation Engineer

Job Description: Hardware Validation Engineer Associate III - Semiconductor S/W Product Development Who... We Are: Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding...

Company: UST
Location: Santa Clara, CA
Posted Date: 15 Oct 2025
Salary: $70000 - 105000 per year

Senior Optical Transceiver Design Engineer

, TIAs, LAs). Signal and power integrity analysis (HFSS, ADS, SI/PI tools). Familiarity with coherent and direct-detect.... What You'll Do Arista Networks is seeking an exceptional Senior Optical Transceiver Design Engineer to join our fast-paced...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 12 Oct 2025

Senior Software Engineer, Aerial - Performance

, debugging and testing skills. Hands-on experience with performance analysis, characterization and optimization. Experience... engineer to drive performance and scalability of our platform. This position offers the opportunity to work on cutting-edge...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Oct 2025

Principal Digital IC Design Engineer

closure, and power optimization. Own RTL delivery milestones from ASR through PRQ, including support for emulation, silicon... Engineer within Custom Silicon Engineering (CCS), you will be part of a high-performance RTL team responsible for architecting...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 09 Oct 2025
Salary: $146850 - 220000 per year

Hardware Validation Engineer

Job Description: Hardware Validation Engineer Associate III - Semiconductor Product Validation Who We Are: Born... digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding...

Company: UST
Location: Santa Clara, CA
Posted Date: 09 Oct 2025
Salary: $65000 - 98000 per year

Senior Optical Transceiver Design Engineer

, TIAs, LAs). Signal and power integrity analysis (HFSS, ADS, SI/PI tools). Familiarity with coherent and direct-detect.... What You’ll Do Arista Networks is seeking an exceptional Senior Optical Transceiver Design Engineer to join our fast-paced...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 08 Oct 2025
Salary: $140000 - 198000 per year

Airflow Infrastructure & Automation Engineer – Silicon Design

of premium devices. Our Qualcomm Oryon™ CPU delivers ultimate performance and power efficiency, featured in Snapdragon® X Series... latest process technology, our CPUs enable best-in-class performance at low power, redefining what's possible for high...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 08 Oct 2025

Principal Physical Design Engineer

timing, power and signal integrity signoff, including IR drop and crosstalk analysis, ensuring designs meet stringent...-performance and low-power goals for Marvell’s optical DSP and networking solutions, supporting multiple business models...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 05 Oct 2025
Salary: $146850 - 220000 per year