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Keywords: Principal Engineer - Design For Test (DFT), Location: Santa Clara, CA

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Principal Engineer - Design For Test (DFT)

and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs The execution involves Design-for-Test... knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design and should be involved in DFT-Architecture definition...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 15 Nov 2025
Salary: $146850 - 220000 per year

Principal Interconnect Micro-architect and RTL Design Engineer

and design Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets... design, Verilog and SystemVerilog Deep knowledge of front-end tools experience with synthesis, static timing, DFT Exposure...

Posted Date: 17 Dec 2025

Senior Principal Digital IC Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Our design team works on state...-of-the-art datacenter and AI SOCs. As a member of the R&D team, you will design world-class hardware for the industry...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Sr. Principal Product Engineer

Expect As a Sr. Principal Product Engineer in Marvell’s AI Connectivity Group, you will lead the productization of cutting... mass production, while collaborating with a global team and coordinating across design, test, foundry, and reliability...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $148190 - 222000 per year

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

checking Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core..., that is predominantly 3rd party IP. What You Can Expect Looking for a talented Principal Technical IP Engineer to join the Marvell Team...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year

Senior Principal Hardware Engineer

throughout the product development lifecycle. Work closely with manufacturing and test teams to ensure DFM/DFT compliance... group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC’s, used...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $164650 - 246700 per year

Lead CPU Firmware Verification and Validation Engineer/ Manager

, and customer satisfaction Contribute to FW architecture and design with a focus on smooth integration and Design For Test (DFT... & customer satisfaction. As a Lead CPU FW V&V Engineer, you will take on a lead technical role, working closely with cross...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 09 Jan 2026