Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience... in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex...
General Summary: In the role of GPU Functional Verification Engineer, your project responsibilities will include the... of GPU pipeline design is a plus, not mandatory Proficiency with formal tools - working knowledge of Property based FV...
General Summary: GPU Functional Verification Engineer In the role of GPU Functional Verification Engineer, your project... below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools...