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Keywords: RTL Design Engineer, Location: Santa Clara, CA

Page: 3

Sr. SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis..., and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowledge...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 08 Jun 2025
Salary: $130600 - 160000 per year

Sr. Engineer, Digital IC Design

provide automotive infotainment and electronic controllers. What You Can Expect Design and implement digital circuits..., and performance. Write and optimize low power Register Transfer Level (RTL) code, implement and simulate digital designs to ensure...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Jun 2025
Salary: $89360 - 133900 per year

Design Verification Engineer, Senior Staff

with architects/RTL engineers to bring-up a new architecture/micro-architecture on the verification environment. Develop testbench... in ASIC and SOC design blocks. Debug failures in tests and root cause issues with test environment and design. Write...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 May 2025
Salary: $124420 - 186400 per year

Architecture Energy Modeling Engineer - New College Grad 2025

We are now looking for an Architecture Energy Modeling Engineer to join our Power Modeling, Methodology and Analysis... become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 07 Aug 2025
Salary: $108000 - 184000 per year

Senior Silicon Engineer

next stage in your career. Responsibilities: Own the micro-architecture specification and RTL development of design modules... Engineer. You will join our front-end silicon team and be responsible for delivering cutting-edge, high performance, low power...

Company: Microsoft
Location: Santa Clara, CA
Posted Date: 07 Aug 2025

CPU Memory Subsystem Verification Engineer

be shown by Apple teams worldwide - Work closely with CPU/SOC/GPU RTL design teams and understand the specification in detail.... In this highly visible role, you will be at the center of a chip design effort collaborating with all fields, with a critical impact...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Aug 2025
Salary: $126800 - 190900 per year

CAD Flow Development Engineer

’s front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and methodology... synthesis, physical design, formal equivalence checking. Experience in other ASIC methodologies such as RTL Lint, CDC, DFT...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Jul 2025

Senior ASIC Clock Engineer

NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work... to see: BSc or MSc degrees in EE or equivalent experience. At least 6+ years of work experience in RTL design, Gate-Level...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Jul 2025

CPU Server Floorplan and Integration Engineer

, you will work with microarchitecture, RTL design and physical design teams to design, floorplan and integrate the CPU designs... solutions that are highly optimized for the needs of the server product. As a CPU Floorplan and Integration Engineer...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 24 Jul 2025

Senior ASIC Power Engineer

We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design... and power efficient RTL to achieve design targets You will be working with architects, designers, verification and VLSI teams...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Jul 2025

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... design and RTL development (SystemVerilog, Verilog). Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence...

Company: Apple
Location: Santa Clara, CA
Posted Date: 23 Jul 2025

CPU Virtual Platforms Engineer

Summary: As a CPU Virtual Platforms Engineer, you will be part of CPU verification team to deliver complex verification... RTL, performance, verification, and SW teams to deliver high speed emulation virtual platforms. Develop, create...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 23 Jul 2025

Senior DFT Engineer

vendor tools Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure... , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jul 2025

VLSI CAD Engineer, ECO Tools - New College Grad 2025

product lines many thousands of times per day. We are seeking a CAD R&D Engineer excited to innovate in algorithms related... as incremental timing and power optimization. A thorough understanding of both VLSI hardware design and efficient software...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Jul 2025

FVCTO - Formal Verification Senior Engineer

and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building... Office). As a Formal Verification Engineer, you will be responsible the following but not limited to: Verify...

Company: Intel
Location: Santa Clara, CA
Posted Date: 13 Jul 2025
Salary: $133050 - 187840 per year

Senior ASIC Synthesis Engineer

: As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks Collaboration... ASIC synthesis and integration. Deep understanding of Verilog RTL design and digital design principles. Proven...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

CPU Implementation Engineer

-offs • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis... implementation. Description As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro...

Company: Apple
Location: Santa Clara, CA
Posted Date: 03 Jul 2025
Salary: $126800 - 190900 per year

Senior DFT Methodology Engineer

of experience in DFT, system architecture, or RTL design. Understanding of fundamental DFT topics, such as, fault modeling, ATPG... including RTL & clocks design, STA, place-n-route and power. Strong programming and scripting skills in Perl, Python or Tcl...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 02 Jul 2025

Principal Static Timing Analysis (STA) Engineer

(PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), RTL Design and other cross... a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Jun 2025
Salary: $124420 - 186400 per year

Senior Reset and Boot ASIC Engineer

. You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. Integrate modules into the overall SOC... of system-level functions like Reset or Chip Boot Solid frontend ASIC design skills, including RTL design, asynchronous...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Jun 2025