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Keywords: RTL Engineer, Location: Bangalore, Karnataka

Page: 5

SMTS Silicon Design Engineer

_ SMTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM... and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges...

Posted Date: 03 Jul 2025

Sr. Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) THE ROLE: The position will involve working with a very... technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills...

Posted Date: 03 Jul 2025

MTS Low power / PTPX Engineer

_ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting..., RTL, PD and power management teams for coming up with the chip low power intent and UPF. Work with architecture, RTL...

Posted Date: 02 Jul 2025

MTS Silicon Design Engineer

_ MTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer...: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs...

Posted Date: 02 Jul 2025

Sr. Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting... management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up...

Posted Date: 01 Jul 2025

High Performance DSP core Implementation Engineer, Sr Lead

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script...

Company: Qualcomm
Posted Date: 29 Jun 2025

ASIC Engineer, Frontend Implementation RDC/CDC

for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end... implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize...

Company: Meta
Posted Date: 29 Jun 2025

ASIC Engineer, Implementation

to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic.... Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation...

Company: Meta
Posted Date: 28 Jun 2025

Design Verification Engineer

our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation... of successful projects, we are committed to excellence and innovation in semiconductor design. Design Verification Engineer - Specialised...

Posted Date: 27 Jun 2025

ASIC Engineer, Design

to deliver comprehensive solutions for various technical domains. ASIC Engineer, Design Responsibilities Architecture... in ASIC (Application-Specific Integrated Circuit) Development Experience in one of these skills: Micro-architecture and RTL...

Company: Meta
Posted Date: 26 Jun 2025

PMTS EMIR convergence Engineer

_ PMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting... management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up...

Posted Date: 26 Jun 2025

DFT PMTS Silicon Design Engineer

_ AECG ASIC DFx - PMTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD... tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues...

Posted Date: 26 Jun 2025

ASIC DV Engineer, Networking

Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure... center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry...

Company: Meta
Posted Date: 26 Jun 2025

Sr Principal Product Engineer

. Position: Sr. Principal Product Engineer Grade: T5 Location: Bangalore Job Description: As a Product Engineer... methodologies and of every stage of the RTL to GDSII flow. Working with timing closure and PPA optimization at 16nm...

Posted Date: 26 Jun 2025

Sr Principal Product Engineer

. Job Description Position: Sr. Principal Product Engineer Grade: T5 Location: Bangalore Job Description: As a Product Engineer... methodologies and of every stage of the RTL to GDSII flow. Working with timing closure and PPA optimization at 16nm...

Posted Date: 25 Jun 2025

Principal Engineer Mixed Signal Verification

, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate..., Mentoring Junior engineer - Partial Ability to lead MSV projects independently Drive enhancements in known methodologies...

Company: Infineon
Posted Date: 25 Jun 2025

Senior Staff Engineer Mixed Signal Verification

, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate..., Mentoring Junior engineer - Partial Ability to lead MSV projects independently Drive enhancements in known methodologies...

Company: Infineon
Posted Date: 25 Jun 2025

Software Principal Engineer - 5G RAN FPGA Verification

Software Principal Engineer The Software Engineering team delivers next-generation application enhancements and new... as a Software Principal Engineer on our 5G RAN FPGA Verification Team in Bangalore. What you’ll achieve As a Software Principal...

Company: Dell
Posted Date: 25 Jun 2025

Senior Staff Chip Verification Engineer

Senior Staff Chip Verification Engineer Job Description In your new role you will: • Lead a team technically... Verilog/UVM test bench components and by integrating3rd party VIP components. Simulate and debug at RTL, Unit Delay, and Gate...

Company: Infineon
Posted Date: 25 Jun 2025

SMTS STA / Synthesis Engineer

_ SMTS SILICON DESIGN ENGINEER(Timing Constraints/STA Signoff Technical Lead) THE ROLE: As a member of the AECG ASIC... development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints...

Posted Date: 21 Jun 2025