_ SMTS SILICON DESIGN ENGINEER(Timing Constraints/STA Signoff Technical Lead) THE ROLE: As a member of the AECG ASIC... Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks...
_ SMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team... RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing...
_ SMTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer... technology nodes Circuit timing/STA, and practical experience with Prime Time or equivalent tools Experience into various sign...