for verification, such as SystemVerilog C++, Java, etc. - Experience with verification methodologies (OVM/UVM) - Highly skilled... partitioned large ASICs - SystemVerilog/C++ co-simulation - Overall knowledge of the ASIC development process - RTL design...
Senior Design Verification Engineer Remote / work from any US location US Citizen or US Permanent Resident preferred... Full-time/employee + Bonus, Benefits, 401k, Stock Options Responsibilities: Develop and execute verification plans...
Senior Design Verification Engineer Remote / work from home US Citizen or US Permanent Resident preferred Full-time.../employee + Bonus, Benefits, 401k, Stock Options Responsibilities: Develop and execute verification plans for digital designs...