Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. ...
Junior engineer - Partial Ability to lead MSV projects independently Drive enhancements in known methodologies...
, Mentoring Junior engineer - Partial Ability to lead MSV projects independently Drive enhancements in known methodologies...
with alternative verification plans, Mentoring Junior engineer - Partial Ability to drive MSV project independently Drive...