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Keywords: Senior High-Performance ASIC Timing Engineer, Location: Santa Clara, CA

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Senior High-Performance ASIC Timing Engineer

. What you'll be doing: Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, GPU... and SOC designs. Owning static timing analysis and convergence of high-performance designs. You will be responsible...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Mar 2025

Senior Staff Physical Design Engineer - Static Timing Analysis

a Senior Staff Physical Design Engineer – Static Timing Analysis (STA) to join our growing team. In this role... Knowledge of data center ASIC architecture or high-performance computing systems Expected Base Pay Range (USD...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 31 May 2025
Salary: $124420 - 186400 per year

Senior ASIC Floorplan Design Engineer

We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer..., interconnect and floorplan improvement opportunities Solve timing and routing congestion issues with physical and ASIC design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 May 2025

Senior ASIC Design Engineer - Memory Controller

We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll... the industry's most complex because of the many protocols that are supported and the stringent requirements of our high...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 05 Apr 2025

Sr Principal ASIC Design Engineer (NetSec)

team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer... and subsystems. Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets...

Location: Santa Clara, CA
Posted Date: 08 Jun 2025

Sr Principal ASIC Design Engineer (NetSec)

team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer... and subsystems. Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets...

Location: Santa Clara, CA
Posted Date: 07 Jun 2025

Senior Staff Engineer, Physical Design

high-performance processor chips. Our custom Processor/ASIC solutions power critical infrastructure in markets... in developing and implementing the physical design flow for Marvell’s high-performance, cutting-edge chips. You’ll work on synthesis...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 11 Jun 2025
Salary: $124420 - 186400 per year

Senior Silicon Engineer

Engineer. You will join our front-end silicon team and be responsible for delivering cutting-edge, high performance, low power..., scalable and programmable DPU silicon. As a Senior Silicon Engineer in the Data Processing Unit team you will be validating...

Company: Microsoft
Location: Santa Clara, CA
Posted Date: 01 May 2025
Salary: $117200 per year

Senior Signal and Power Integrity Engineer

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two... design problems. System-level power integrity simulations of high-performance AI systems, graphic cards, and Tegra systems...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Apr 2025

Senior Signal and Power Integrity Engineer - Hardware

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two.... System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, LP5X and other interfaces...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 13 Apr 2025

Senior FPGA Prototyping Engineer - Hardware

performance of the prototype, analyze timing and generate bit streams. Bring up the design on FPGA prototyping platforms... is desirable Prior experience with hardware emulation or prototyping (Synopsys HAPS, Zebu, Mentor Veloce) of a high-performance...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

Senior Low Power Integration Engineer

, Python, tcl. NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance... solutions and WARs through lab experimentation and effective use of debug tools, to achieve high product quality at extremely...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Jun 2025

SoC Design Engineer

; Machine-learning, AI; FPGA. Title: Engineer (mid-senior career) Location: Santa Clara, CA. Hybrid. Relocation assistance...We seek a skilled front-end SoC design engineer. A customer driven professional with a track record of effective...

Posted Date: 31 May 2025