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Keywords: Senior I/O Subsystem Architect, Location: Santa Clara, CA

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Senior I/O Subsystem Architect

We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 01 Feb 2026

Senior Principal Memory Architect

. As a Senior Principal Memory Architect, you will play a key role in defining and delivering memory subsystem solutions that power..., and cloud workloads. What You Can Expect Architect high-performance HBM/DDR memory subsystems for Marvell’s custom compute...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

Senior GPU Memory Architect

architect to contribute to the development of future high-performance GPU computing systems. Ideal candidates...: Define and architect innovative features for next-generation GPU memory and on-chip interconnect subsystems. Develop...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 Dec 2025

Senior System Architect, GPU

a motivated system architect to define future aspects of our GPU through employing pioneering technologies. Your role... crowd: Experience with GPU architecture, especially in off-chip IO, memory subsystem, and/or Network-on-Chip (NoC...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 Nov 2025

Senior Performance Architect

state in silicon domain subsystem and defines the technology roadmap for the same based on hardware features, requirements... for the technology domain. As a senior engineer, recognized as a domain expert who influences and drives technical direction...

Company: Intel
Location: Santa Clara, CA
Posted Date: 15 Jan 2026

Senior Electrical Engineer

of America Job Description: Johnson & Johnson, Robotics and Digital Solutions (RAD) group is recruiting for a Senior... and be part of the success of our mission. Core Job Responsibilities: Architect, integrate and test an embedded Acoustic...

Location: Santa Clara, CA
Posted Date: 28 Jan 2026
Salary: $115000 - 197800 per year

Senior ASIC RTL Design Engineer

: RTL design of high speed design, clock/reset/power features, IP Integration, sub-system level design Architect... aspects of the overall design of the IP and the subsystem. Work closely with FEINT, DFT, Physical Design and SOC teams...

Posted Date: 26 Dec 2025