RESPONSIBILITIES: As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: Write microarchitecture... your career. THE ROLE: A senior technical contributor that drives end-to-end delivery of SerDes solution directly contributing...
Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog...
Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog...