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Keywords: Timing Signoff Technical Lead, Location: Bangalore, Karnataka

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Timing Signoff Technical Lead

such as Static Timing Analysis, Formal Verification, EM/IR/PDN aspects, Layout Verification, etc. The candidate..., size/complexity of products and the size of the team. The ideal candidate will have the skills and experience to lead SoC...

Company: Intel
Posted Date: 20 Dec 2025

STA/Timing Methodology Engineer(Senior/Lead)

, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug...+ years of Hardware Engineering or related work experience. Overview: Experienced STA/Timing Engineer with 8-12 Years...

Company: Qualcomm
Posted Date: 19 Dec 2025

Technical Lead I - VLSI

– 2 3. Designation/ band – Technical Lead I – VLSI – B1 4. Mandatory Skill – RTL Design Lead 5. Location – Bangalore JD.../Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams...

Company: UST
Posted Date: 04 Dec 2025

Technical Lead I - VLSI PD CAD

floorplanning, placement, clock tree synthesis (CTS), and routing.  Familiarity with timing closure and DRC/LVS signoff.../Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams...

Company: UST
Posted Date: 17 Dec 2025

Technologist, ASIC Development Engineering (Design Lead - High-speed IO)

support and review and provide support for post-TapeOut activities such as Silicon characterization . Provide good technical... leaders Should have architected and lead high speed interface design solutions from specification through Silicon debug...

Company: SanDisk
Posted Date: 14 Jan 2026

Logic Design Lead - Power Management

Guide and mentor junior engineers. Represent as Power Lead in various forums. Signoff the Pre-silicon Design that meets.... Your role and responsibilities As Logic Lead for Power Management, you will be responsible for design and development...

Company: IBM
Posted Date: 11 Jan 2026

Lead Full chip Soc Sign off & EMIR closure Engineer

like Ansys Redhawk on EMIR, PT-PX for Power signoff and Primetime for Timing Should have worked as a go to person or technical... choices. Familiarity with DFx and scan architecture for EMIR considerations. Technical Leadership Define EMIR signoff...

Posted Date: 10 Jan 2026

Physical Design Lead

, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . Role Overview The Lead... Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role...

Posted Date: 09 Jan 2026

Lead Logic Design Engineer - Core Units Front end platform

with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon... better decisions quicker on the most trusted hardware platform in today's market. Your role and responsibilities Lead the...

Company: IBM
Posted Date: 11 Dec 2025

Display Synthesis Sr/Lead/Staff

strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain... and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate...

Company: Qualcomm
Posted Date: 20 Nov 2025

Power Convergence Lead Physical Design

for Timing, Ansys Redhawk on EMIR, PT-PX for Power signoff Should have worked as a go-to person or technical lead... Design, Timing Analysis, Synthesis, Logical equivalence, Physical Verification, Power design/implementation/signoff...

Posted Date: 17 Nov 2025

Lead MTS Physical Design

an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working...: * Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode...

Company: Rambus
Posted Date: 31 Oct 2025

Physical Design Lead

, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis... Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical...

Posted Date: 30 Dec 2025

Lead Physical design, Physical Implementation, STA

, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis... analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical...

Posted Date: 08 Nov 2025

Principal Engineer - SOC Clocking

Job Details: Job Description: Key Responsibilities: Lead the architecture, design, and integration of SoC-wide... with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical...

Company: Intel
Posted Date: 15 Jan 2026

Senior Logic Designer - Fabric

feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up.... Your role and responsibilities As a Logic design lead in the IBM Systems division, you will be responsible for the micro...

Company: IBM
Posted Date: 12 Jan 2026

Staff Engineer Digital Design Engineer

-Electronics Location : Bangalore, India Job Grade : P4 Rssponsibilities: Lead and develop timing methodologies, establish... technical guidance to elevate team proficiency and performance. Desired Skills: Proven ability in timing analysis...

Posted Date: 18 Dec 2025

Associate III - VLSI DFT_N

/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025

Staff Engineer Digital Design Engineer

-Electronics Location : Bangalore, India Job Grade : P4 Rssponsibilities: Lead and develop timing methodologies, establish... technical guidance to elevate team proficiency and performance. Desired Skills: Proven ability in timing analysis...

Posted Date: 17 Dec 2025

Associate III - VLSI STA

/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025