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Keywords: ASIC Design Engineer - Design & Timing Constraints, Location: San Jose, CA

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ASIC Design Engineer - Design & Timing Constraints

/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups... to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 24 Apr 2025

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 06 Jun 2025

STA Design Engineer (Static Timing Analysis)

_ THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring... in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints...

Posted Date: 20 Apr 2025

Senior ASIC Design Engineer

coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug... in the lab Minimum Qualifications: Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 06 Jun 2025

ASIC Engineering Technical Leader - SDC

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 02 Apr 2025

Sr. Silicon Design Engineer

and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations Low power design techniques..._ SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer...

Posted Date: 29 May 2025

IC Design Engineer

. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with the physical... and excellent academic standing. 2). Must have in-depth knowledge of IC technology, ASIC design flows, EDA tools and Physical...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Apr 2025

STA Engineer

: Working with Genus tools (Cadence) for design synthesis including DFT flow, Review timing and constraints reports. Running...Broadcom is looking for a senior level STA engineer. In this highly visible role you will be working on various ASIC...

Company: Broadcom
Location: San Jose, CA
Posted Date: 09 May 2025
Salary: $119000 - 190000 per year

Staff R&D Engineer Adv Tech Dev

for IP & ASIC to create robust designs in line with advanced semiconductor and packaging process flows & constraints Work... closely with technology experts and Silicon manufacturing teams to deploy the technology requirements for ASIC product design...

Company: Broadcom
Location: San Jose, CA
Posted Date: 12 Apr 2025
Salary: $119000 - 190000 per year