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Keywords: ASIC Physical Design and Timing Engineer, Location: Santa Clara, CA

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ASIC Physical Design and Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic.... What you'll be doing: Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Sep 2025
Salary: $108000 - 184000 per year

Senior ASIC Physical Design Engineer, Netlisting

, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer... quality checks, etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Oct 2025

Senior Timing CAD Engineer, Applied AI

for EDA, semiconductor, or complex data domains .Strong background in VLSI/ASIC design — with deep understanding of timing... reasoning to accelerate design closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Oct 2025

Sr. Staff Static Timing Analysis (STA) Engineer

Physical Design team at Marvell in Santa Clara is seeking a Sr. Staff Static Timing Analysis (STA) Engineer to contribute... physical design strategies, methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $124420 - 186400 per year

ASIC Design Engineer

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA... with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA SOC...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Oct 2025
Salary: $108000 - 184000 per year

ASIC Floorplan Design Engineer - New College Grad 2025

, interconnect and floorplan improvement opportunities Solve timing and routing congestion issues with physical and ASIC design...We are now looking for a ASIC Floorplan Design Engineer - NCG. NVIDIA is seeking a talented ASIC Floorplan Engineer...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Oct 2025
Salary: $96000 - 161000 per year

Senior Video ASIC Design Engineer

We are now looking for a Senior Video ASIC Design Engineer! NVIDIA has been transforming computer graphics, PC gaming..., functional coverage definition, synthesis, power, timing, and area optimization, static checks, and support of physical design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Oct 2025

ASIC/RTL Design Engineer - Senior (San Jose, Ca) - AMDJP00004484

Position Title: ASIC/RTL Design Engineer Location: Santa Clara, CA Position Status: Contract Pay Rate: 75/hr... closure, Interfacing with physical execution, software, and silicon bring-up teams. EXPERIENCE AND EDUCATION: - SoC Design...

Company: Seneca Resources
Location: Santa Clara, CA
Posted Date: 25 Sep 2025
Salary: $75 per hour

Senior ASIC Design Engineer - Circuits

We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit... with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis Strong team player...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 27 Aug 2025

Senior ASIC Design Engineer – Clocks IP

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team... ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jul 2025

Senior ASIC Design Engineer

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU... with verification engineers. Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Jul 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications 10 + years of full time ASIC..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications 3+ years of full time ASIC..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications In-depth knowledge of memory..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $126800 - 190900 per year

Principal Networking ASIC Design Architect

and deploy end to end power optimization methodology for Physical Design Implementation Define PVT corners, device frequency... and strong collaboration across multiple business units PREFERRED EXPERIENCE: Deep experience in physical design and methodology preferred...

Posted Date: 17 Aug 2025

Senior Reset and Boot ASIC Engineer

NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously.... What you’ll be doing: Be an integral part of the System ASIC Design team to help with the Micro-architecture definition...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 01 Oct 2025

ASIC Implementation Engineer - PnR & FE

. Experience with SOC design integration and Front-end implementation. Knowledge of Timing/physical libraries and memories... a highly motivated and experienced ASIC Implementation Engineer to join our dynamic team. The ideal candidate...

Posted Date: 04 Sep 2025

GPU Top Level Physical Design Engineer

Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle...) Preferred Qualifications Experience with hierarchical design approach, top-down design, budgeting, timing and physical...

Company: Apple
Location: Santa Clara, CA
Posted Date: 12 Sep 2025

Senior Logic Design Engineer– Physical Design

We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design... with the physical design team on implementation, synthesis and timing closure as well as working on micro-architectural...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Sep 2025

Principal Silicon Design Engineer

design team and physical design team for large scale ASIC chip physical implementation Drive design and methodology... Timing closure for high-speed designs. CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python...

Posted Date: 20 Sep 2025