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Keywords: ASIC Physical Design and Timing Engineer, Location: Santa Clara, CA

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ASIC Physical Design and Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic.... What you'll be doing: Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Sep 2025
Salary: $108000 - 184000 per year

Senior ASIC Physical Design Engineer, Netlisting

, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer... quality checks, etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Oct 2025

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

and Physical design teams responsible for achieving timing, area, performance and power goals of the unit. Help define the... or other related high-performance semiconductor designs. Physical design expertise including hands-on synthesis experience, timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Nov 2025

Senior Timing Methodology Engineer

, self-heating, thermal impact, IR drop etc. Collaborate with technology leads, VLSI physical design, and timing engineers... To See: MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior Timing CAD Engineer, Applied AI

for EDA, semiconductor, or complex data domains .Strong background in VLSI/ASIC design — with deep understanding of timing... reasoning to accelerate design closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Oct 2025

Sr. Staff Static Timing Analysis (STA) Engineer

Physical Design team at Marvell in Santa Clara is seeking a Sr. Staff Static Timing Analysis (STA) Engineer to contribute... physical design strategies, methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $124420 - 186400 per year

ASIC Clocks Design Engineer - New College Grad 2025

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team... ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Dec 2025
Salary: $108000 - 184000 per year

Senior ASIC Design Engineer

We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA... limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior ASIC Design Engineer – Clocks IP

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team... ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications 10 + years of full time ASIC..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications 3+ years of full time ASIC..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications In-depth knowledge of memory..., we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $126800 - 190900 per year

Senior Reset and Boot ASIC Engineer

NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously.... What you’ll be doing: Be an integral part of the System ASIC Design team to help with the Micro-architecture definition...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 01 Oct 2025

Principal Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance.... You will work with both local and global team members on the physical design of complex chips and lead the development of advanced...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $146850 - 220000 per year

Senior Principal Engineer, Physical Design

advanced physical design methodologies and flows Strong knowledge on static timing analysis (PrimeTime, Tempus), EM/IR-Drop... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior Staff Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance.... What You Can Expect You will work with both local and global team members on the physical design of complex chips as well as the...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance.... What You Can Expect You will work with a global team on both the physical design of complex chips as well as the methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $89360 - 133900 per year

Physical Design Methodology Engineer

collaterals PREFERRED EXPERIENCE: Experience in ASIC Physical Design and/or CAD development Hands-on experience with Place... related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams...

Posted Date: 09 Nov 2025

Physical Design Engineer Intern - Bachelor's Degree

, Static Timing Analysis, Physical Verification, etc.). What You Can Expect One or more of the following: Block lever... floorplan, place and route, timing analysis/closure, ECO implementation. Power grid or custom route. Physical verifications...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025
Salary: $27 - 55 per hour

Principal Silicon Design Engineer

design team and physical design team for large scale ASIC chip physical implementation Drive design and methodology... Timing closure for high-speed designs. CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python...

Posted Date: 20 Sep 2025