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Keywords: DDR Design Verification Engineer, Location: Santa Clara, CA

Page: 1

DDR Design Verification Engineer

your career. THE ROLE: We are looking for an experienced Verification Engineer to join our team as a Technical Lead... for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR...

Posted Date: 07 Nov 2025

ASIC Design Verification Engineer (Santa Clara, CA)

and products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team.../assertion based verification technologies Experience in verifying complex SOC or SOC subsystems Experience with caches and DDR...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 22 Nov 2025
Salary: $126700 - 190100 per year

SOC Design Verification Engineer

"Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential TMR ID: # JYTONZ Role: SOC Design Verification.... Experience in development of UVM based verification environments from scratch. Experience with Design verification of Data...

Posted Date: 01 Nov 2025

FPGA Design Engineer

an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC/MPSoC platforms and practical experience in camera... buffers, DDR and high-speed IO. Good knowledge of digital electronics, schematics, and board-level design...

Location: Santa Clara, CA
Posted Date: 28 Nov 2025
Salary: $124000 - 171000 per year

Memory PHY RTL Design Engineer

your career. THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory...

Posted Date: 13 Nov 2025

Digital, Mixed Signal IC Design Engineer, Principal

other chip companies and big tech companies, familiar names to all candidates. What You Can Expect ASIC design engineer... responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $146850 - 220000 per year

Analog Design Engineer

and timing analysis, and reliability checks. Interface with cross-functional teams like RTL, Verification and Physical Design... and implementation of high speed and high precision memory interface PHY circuits for DDR, LPDDR and GDDR. This team owns a wide variety...

Posted Date: 09 Dec 2025

Senior Staff Physical Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Physical Design team... is located in our Santa Clara, CA office, and has a long history of successful design tapeouts in advanced process nodes...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 21 Nov 2025
Salary: $124420 - 186400 per year

GPU Prototype and Validation Engineer, Staff

of practical experience Design Verification knowledge - UVM/System Verilog preferred Knowledge of GPU/CPU/DDR/Bus preferred... methodology to improve the area/performance of the synthesized FPGA RTL. System level RTL simulation & design verification...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 05 Dec 2025

RTL Engineer

, CA (onsite) About the Role Role Overview: We are looking for a highly skilled RTL Design Engineer to join our hardware.... Collaborate with verification teams to define test plans, review coverage, and debug design issues. Support validation and bring...

Company: Qualitest
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $120000 - 130000 per year

RTL Engineer Lead

, CA (onsite) About the Role Role Overview: We are looking for a highly skilled RTL Design Engineer to join our hardware.... Collaborate with verification teams to define test plans, review coverage, and debug design issues. Support validation and bring...

Company: Qualitest
Location: Santa Clara, CA
Posted Date: 27 Nov 2025
Salary: $140000 - 160000 per year

Principal Technical IP Engineer

required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design.... • Functional Verification Support: Provide integration-level support to design verification teams, including simulation bring-up...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $126800 - 190900 per year

Senior DFT Methodology Engineer

, as well as verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll... with 2+ years of experience in DFT, system architecture, or RTL design. Understanding of fundamental DFT topics...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Oct 2025